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Intel's Kentsfield CPU (top) will be the first quad core desktop chip, Clovertown will be the server equivalent - Courtesy AnandTech.com
According to Intel, it says quad-core for desktops will be ready by 2007

IDF is definitely showcasing a host of exciting technologies, but today Intel showed details of some very interesting technology in regards to where servers and desktops will be heading in 2007. According to company slides, Intel expects to be shipping multi-core Xeon processors based on the Montecito core by mid-year 2006. Targeting the MP segment, Intel's next-generation Tulsa processor will be manufactured using 65nm fabrication technology with large 16MB caches.

For the desktop segment, Intel indicated that Kentsfield will be the first quad-core processor and will be released in Q1 of 2007 after Conroe. During mid-year 2006, Intel will introduce its Bridge Creek platform but it did not indicate whether or not it will be Kentsfield ready. Recently, AMD also indicated that it will be introducing quad-core processors in 2007 for the server segment, but did not talk about the desktop space. According to Intel slides, Kentsfield will be focused on immediately after Conroe.

Intel indicated that quad-core processors will only be needed for the very highest-end desktops. Corporate users and enterprise level productivity software will also be a target for Kentsfield. Tigerton, Intel's quad-core MP processor, will also be released in early 2007.


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What OS'es will support this CPU??
By SpaceRanger on 3/8/2006 4:17:28 PM , Rating: 2
Everywhere I look on the internet, I see references to XP's CPU support as:

Desktop PCs.
Home Edition - 1 Physical Chip * Which could be a Hyperthreaded Intel and appears to XP as two independent processors

Professional - 2 Physical Chip(s) * Each using HT, maxing out at 4 processors -or- Two MutliCore CPU's with 4 Physical cores.

Now, if these quad-core CPU's offer HT, that would be 8 overall processors needed to be recognised. Would XP or Vista support this (without having to get an expensive license)??




RE: What OS'es will support this CPU??
By A5 on 3/8/2006 4:20:14 PM , Rating: 2
Probably another "wonderful" reason to upgrade to Vista ;)


RE: What OS'es will support this CPU??
By zsdersw on 3/8/2006 4:46:51 PM , Rating: 2
HyperThreading is on its way out. I wouldn't expect to see it in Conroe/Merom/Woodcrest or anything that comes after.


RE: What OS'es will support this CPU??
By TomZ on 3/8/2006 5:28:58 PM , Rating: 2
Wrong - hyperthreading is in the roadmap for all these processors. Intel stated that only the high-end models would have hyperthreading.


By JackPack on 3/8/2006 5:33:53 PM , Rating: 2
No, there is no HTT in this generation.

It will return in the generation after Conroe/Woodcrest.


RE: What OS'es will support this CPU??
By masher2 (blog) on 3/8/2006 10:31:01 PM , Rating: 2
Merom, Conroe, Woodcrest-- all do not have HT. While it may return in the generation after this, I strongly suspect its going to be in a radically different form.


RE: What OS'es will support this CPU??
By TheLiberalTruth on 3/9/2006 9:43:31 PM , Rating: 3
Why would HT even help? I was under the impression that HT was only useful for when the long pipeline of Northwood or the never-ending pipeline of Prescott stalled, eh?


RE: What OS'es will support this CPU??
By Questar on 3/10/2006 9:41:10 AM , Rating: 2
SMT (let's call it by it's proper name) will help a great deal. This CPU has 4 execution units that need to be kept fed. SMT will do a great deal to keep those units running.

SMT will be enables in the next spin of Conroe and it's bretheren.

Just like it was in the P4 line and just needed to be enabled, it's in Conroe.


RE: What OS'es will support this CPU??
By Viditor on 3/10/2006 11:27:23 AM , Rating: 2
quote:
SMT (let's call it by it's proper name) will help a great deal. This CPU has 4 execution units that need to be kept fed. SMT will do a great deal to keep those units running


Hmmm...

1. HT is a form of SMT, so HT really is it's proper name.
2. Having more execution units makes HT LESS useful, not more so. HT (stated rather simply) allows sharing of execution units...


RE: What OS'es will support this CPU??
By Questar on 3/10/2006 3:37:22 PM , Rating: 2
Wrong.

1. HT is a trade name for SMT.

2. It's very possible - even common - for one ALU to be stalled wating for another ALU to complete it's work or waiting for memory access(depending upon how good the scheduler and prefetch algorithms are). SMT will allow the stalled ALU to do other work while it's waiting.


RE: What OS'es will support this CPU??
By Viditor on 3/10/2006 8:31:26 PM , Rating: 2
Sigh...time to teach again? :)

1. HT is a branded methodology for performing SMT. IBM uses a slightly different methodology to perform SMT on the Power5...it's not HT, but it is SMT.

2. You have just proven MY point...Conroe has 4 ALUs! The fewer execution units you have, the more important it is that each is more efficient. Conroe has double the execution units of Netburst, which means that the stalled ALU will not effect the work done to anywhere near the degree that it would on the Netburst architecture. Athlon has 3 execution units, and SMT was found to be more of a hindrance than a help on the Athlon architecture...imagine what the effect would be on 4.


RE: What OS'es will support this CPU??
By Knish on 3/11/2006 12:08:54 PM , Rating: 2
By Viditor on 3/11/2006 7:33:24 PM , Rating: 2
Woops...good call and thanks for the correction!


RE: What OS'es will support this CPU??
By defter on 3/12/2006 1:56:01 PM , Rating: 2
quote:
2. You have just proven MY point...Conroe has 4 ALUs! The fewer execution units you have, the more important it is that each is more efficient. Conroe has double the execution units of Netburst, which means that the stalled ALU will not effect the work done to anywhere near the degree that it would on the Netburst architecture. Athlon has 3 execution units, and SMT was found to be more of a hindrance than a help on the Athlon architecture...imagine what the effect would be on 4.


SMT isn't implemented just because of stalls. The more execution units you have, the harder is to keep them fed using only one thread. That's why Power5, which issue 8 instructions and execute 5 per cycle, has SMT.


RE: What OS'es will support this CPU??
By Viditor on 3/13/2006 9:30:03 AM , Rating: 2
quote:
SMT isn't implemented just because of stalls. The more execution units you have, the harder is to keep them fed using only one thread. That's why Power5, which issue 8 instructions and execute 5 per cycle, has SMT

But, there is a big difference between IBM's SMT and Intel's HT...for one thing, the Power5's SMT can be shut off dynamically and the resources reassigned on the fly. HT is nowhere near that sofisticated yet...


By Questar on 3/13/2006 9:49:47 AM , Rating: 2
So?


RE: What OS'es will support this CPU??
By koinkoin on 3/8/2006 4:52:37 PM , Rating: 2
No you don't need to change, Microsoft is using the sockets and not cores for the licensing.

If you look today a dual core Xeon with HT gives you a total of 8 virtual cpus under windows. And it Works with XP Pro.

The question, does Conroe actually support HT? Or has it been dropped?
I mean HT is a good technology, but it is my opinion not that interesting anymore with multi core processors.


RE: What OS'es will support this CPU??
By phaxmohdem on 3/8/2006 7:44:48 PM , Rating: 2
I don't see why they would need it.... Hyperthreading was created as sort of an enhancement for the Netburst architecture, which as we all know suffers greatly in the case of pipeline stalls. Hyperthreading keeps feeding the CPU during these times to both reduce latency, and help in processing simultaneous threads..

This whole argument has been gone over before, when people asked whether or not the A64 architecture would benefit from such technology as HyperThreading, and the consensus seems to be that it would not see any drastic or practical gains, due to its short pipeline length, and efficiency as-is. The number escapes me.. but 15 pipelines?? (A64) is a lot easier to recover from than having to flush out 31 different stages (P4 Prescott) I don't see why Conroe which is based on Pentium M as we all know (~15 pipes) would benefit from HT.


By defter on 3/12/2006 1:51:07 PM , Rating: 2
quote:
The number escapes me.. but 15 pipelines?? (A64) is a lot easier to recover from than having to flush out 31 different stages (P4 Prescott) I don't see why Conroe which is based on Pentium M as we all know (~15 pipes) would benefit from HT.


Pipeline length has vert little to do with benefits of SMT. For example Sun Niagara has 6 stage pipeline and it supports 4-way SMT. It definately benefits from SMT.


By smitty3268 on 3/8/2006 5:00:00 PM , Rating: 2
XP Pro might support it, but I wouldn't count on anything less than Vista Business or Home Premium editions. Since Vista is supposed to be out by the time this chip launches anyway. I'm sure the 2 cheapest versions of Vista won't support it.


By TomZ on 3/8/2006 5:29:49 PM , Rating: 2
I'm sure Microsoft will update the license based on quad-core, as they did when dual-core processors first became available.


Is Super Glue included ?
By cornfedone on 3/8/06, Rating: 0
RE: Is Super Glue included ?
By Questar on 3/8/2006 7:54:35 PM , Rating: 3
Something I learned is sales:

Whenever you make a statement, always ask yourself "So what?".


RE: Is Super Glue included ?
By ChronoReverse on 3/8/2006 8:23:54 PM , Rating: 2
Indeed. It's still four physicak cores on one die so why is it not a quad-core?

Furthermore, each pair is using a shared cache which is superior to even AMD's point connections.


RE: Is Super Glue included ?
By Xenoterranos on 3/9/2006 1:28:26 AM , Rating: 2
Ok smarty. All four cores on an AMD quad core chip could talk to each other without a single iota's detriment to speed or efficiency. In this frankenstein 4 core thing intel has made, only the cores that are physically conneced can "talk" to eachother via the shared cache; for each pair of cores to talk to the other pair of cores requires traversing the FSB, ie, no better than the frankencore Pentium D's.


RE: Is Super Glue included ?
By JackPack on 3/9/2006 3:04:09 AM , Rating: 2
Having two separate dice allows Intel to mix and match parts with different TDPs and not waste any cores. AMD's solution means low yields. Good luck to AMD finding four adjacent cores all operating at the same speed and TDP with minimal defects.

AMD's solution may be slightly better, but it's pointless if it costs $1500 per chip. Why do you think Intel is offering an Extreme Edition part based on quad-core Kentsfield while AMD isn't offering any quad-core for the desktop?


RE: Is Super Glue included ?
By PrinceGaz on 3/9/2006 5:47:33 AM , Rating: 2
"two seperate dies" is the correct term, not "two seperate dice". The plural of die is dies when talking about CPUs and other manufacturing processes, and dice when talking about cubes (and other polyhedrons) used in games of chance.


By KristopherKubicki (blog) on 3/9/2006 8:24:06 AM , Rating: 2
RE: Is Super Glue included ?
By Viditor on 3/11/2006 7:51:52 PM , Rating: 2
quote:
Good luck to AMD finding four adjacent cores all operating at the same speed and TDP with minimal defects

I don't know...they seem to have had no problem with the same thing on dual core, and their yeilds are extraordinarily high.


By ChronoReverse on 3/9/2006 5:38:17 PM , Rating: 2
So that makes it... still a quad core chip. Your point?

In any case, each pair talks to each other even better than with a point-to-point connect. Futhermore, our very own Anandtech has shown that the benefits from the AMD solution (while theoretically much better) don't seem to (currently) translate to measureable performance boosts (on the desktop level).

Which, frankly, isn't surprising on the desktop level. How many tasks can you think of would use multiple cores with huge inter-thread communications? On server systems definitely, on desktops not so much.


Don't get me wrong, I like AMD, all of my machines are either AthlonXPs or Athlon64s. My last Intel CPU was a Pentium 3.

But if Intel has the better CPU in 2007 (my next upgrade time) with a price/performance better than AMD, there is absolutely no reason I wouldn't buy it.


RE: Is Super Glue included ?
By Viditor on 3/9/2006 6:26:29 PM , Rating: 2
quote:
Furthermore, each pair is using a shared cache which is superior to even AMD's point connections

This touches on the problem...I/O.
A large part of the reason that Smithfield and the other MCM dual cores don't perform nearly as well as the X2 (or Conroe for that matter) is that they must communicate with each other through the FSB. The quad core Intel is announcing for the desktop will have a few familiar problems (IMHO):

1. It will still use the MESI (Modified Exclusive Shared Invalid) cache coherency protocol, which has a greater latency penalty than the MOESI (Modified Owner Exclusive Shared Invalid) protocol that AMD uses.

2. Cache coherency between the modules will need to go through the FSB, and considering all of the other data is going through the FSB as well, this is going to have to be a much faster and wider FSB (or even 2 FSBs) than Intel has announced on any of their current models.

3. Based on current Conroe specs, a quad core desktop will have to have:
a. 8 to 16 MB of cache (which would make it about the size and cost of Alaska), or
b. Less cache/core, which will hit performance fairly hard, or
c. Move to an L3 cache model, which is a completely new design...


RE: Is Super Glue included ?
By Viditor on 3/9/2006 6:32:59 PM , Rating: 2
I need to read more...I guess the answer is "3a". 16MB of cache is absolutely massive! This means that ~75% of the die will be nothing but L2!


RE: Is Super Glue included ?
By ChronoReverse on 3/9/2006 6:57:38 PM , Rating: 2
Indeed. While I'm not exactly a big fan of that, if it works AND Intel prices it reasonable, I can live it. Obviously it won't be at first, but it's not like I need quad-cores right either (our servers are small enough that dual processors are quite enough thank you).


RE: Is Super Glue included ?
By Viditor on 3/10/2006 11:45:34 AM , Rating: 2
quote:
if it works AND Intel prices it reasonable, I can live it

Price is a good point...
I don't know if you remember, but AMD signed a license with ISI at the end of last year for SOI cache made using Z-Ram.
Z-Ram gets 5 times the density of normal cache (and only works with SOI). In addition, it utilizes far less power than normal cache memory...
Imagine a quad core Opteron that has only a 50% increase in footprint vs dual core at the same node, but has double the cache and double the cores...and uses the same power.
Add to that AMD's new strained silicon process, and I think we will see AMD keep the server crown for awhile...at least until their nextgen chips come out.


RE: Is Super Glue included ?
By Questar on 3/10/2006 4:28:09 PM , Rating: 2
So what's the problem? The performance of a top end Porche is generated 85% by air. Is that bad?

Quit trying spread FUD. It doesn't matter how performance is created as long as it exists.


RE: Is Super Glue included ?
By Questar on 3/10/2006 3:43:12 PM , Rating: 2
2. Thanks to cache partitioning coherency mostly becomes a non-issue. You don't know how much traffic will be traveling over the FSB, so you can't say how wide or fast it will need to be.


RE: Is Super Glue included ?
By Viditor on 3/11/2006 7:46:57 PM , Rating: 2
quote:
Thanks to cache partitioning coherency mostly becomes a non-issue

You should go back and read the posts again...
Cache partitioning only occurs within each die. The quad cores will have 2 dice per CPU, so coherency must be maintained via the FSB!
While I can't say how much traffic there will be (nor can I answer "how long is a piece of string"...), if you're going to actually USE the 4 cores it should be at least double that of a dual core...QED. In addition, the quad core must use the same FSB for coherency between dice...


RE: Is Super Glue included ?
By Questar on 3/12/2006 9:02:10 PM , Rating: 2
Your first false assumtion is that both L2 caches must always be coherent. They only must be cohent for data that resides in both caches - in other words in threads that sharing resource amomgst the cores. Independent threads do not need their written data sent to the other cache.

We can go on and on about other things, such as how all memory writes must transverse the FSB anyway and we really don't have any idea what - if any - impact cache updates have.

So we will just wait and see in a few months.


RE: Is Super Glue included ?
By Viditor on 3/15/2006 8:47:45 AM , Rating: 2
quote:
Your first false assumtion is that both L2 caches must always be coherent


I don't think I made that assumption...
I'll quote from a white paper done at Berkely:

"Not surprisingly, we find that caches are effective at reducing the processor traffic to memory. We observe improvements in L2 cache miss rates for L2 cache sizes up to 1 MB, the largest available for this processor. While larger caches are effective, this benefit is not without con-sequences. Coherence traffic, in the form of cache misses to dirty data in other processors’ caches, increases as caches get bigger, and as the number of processors increases. We find that the exclusive state of the four-state MESI cache coherence protocol is under-utilized for multi-processor configurations, and could likely be omitted in favor of a simpler three-state protocol. Finally, multipro-cessor scaling of this workload is good, but even modest memory system utilization degrades application memory latency, limiting database throughput..."

http://www.hpl.hp.com/personal/Kimberly_Keeton/Ber...


RE: Is Super Glue included ?
By Questar on 3/10/2006 4:33:21 PM , Rating: 2
Oh and by the way, I do want to commend you on your argumentative skills. If I hadn't taken logic classes myself, I could have fallen for some of your arguments.

You have been very skillful in taking a P4 argument and applying it to Conroe. Of course they fall apart because you don't know the Conroe architechure.


RE: Is Super Glue included ?
By Viditor on 3/11/2006 7:48:42 PM , Rating: 2
quote:
You have been very skillful in taking a P4 argument and applying it to Conroe. Of course they fall apart because you don't know the Conroe architechure

And yours have fallen apart because we aren't talking about Conroe... :)


RE: Is Super Glue included ?
By TomZ on 3/8/2006 9:24:57 PM , Rating: 2
What's your point? Presler is two single-core processors in a single package. What is doing this with four any different? This is just a modular packaging concept: make all the dies the same, and then put 1, 2, or 4 into a particular product's package.


By Doormat on 3/8/2006 4:23:13 PM , Rating: 2
Intel has made it quite obvious that they do plan on offering quad core chips for desktops, and I see Apple lining up. Maybe thats why its taking so long to rewrite the "pro" apps - optimizing them for as many threads as the hardware can provide.




One Year From Now.
By Questar on 3/8/2006 4:40:29 PM , Rating: 2
Holy Crap. CPU's on six month release schedules. I'm amazed.




By RyanHirst on 3/9/2006 5:25:48 PM , Rating: 2
Nobody has quite hit the relevant point on the head. "Dice" is Correct (with a capital). Oh, yes, and "dies" is Correct, too. Both follow the formal definitions, neither is a product of casual or lax usage. The point is:
While "dies" is a correct plural for mechanical procedures that involve stamping, etching or shaping objects, it refers to the machine that does the stamping. The softer (or resultant) objects which have been stamped by the dies may, if cuboid, be called dice. Regardless of what you remeber from classrooms, cuboids are properly "dice" only if they are cut from something larger; cuboids are properly "dies" by definition, cf. the use in architecture to describe blocks used as part of a larger structure.
Since the specific connotation of "dice" is a cuboid that is cut from a larger whole, and the specific connotation of "dies" is that which performs the stamping, cutting or engraving-- dice is the most logically correct.
Look at it this way: They are dice when they are made and cut. When on their way to being integrated into a complete processor chip (with heatspreader, pins, etc.) they are dies. Of course they're either and both, whenever you want.
Carry on.
[All definitions taken from the Oxford English Dictionary]




Intel Talks...
By Beenthere on 3/10/06, Rating: -1
RE: Intel Talks...
By Questar on 3/11/2006 11:28:20 AM , Rating: 2
This, folks, you why you should make sure your children stay in school.


RE: Intel Talks...
By Viditor on 3/11/2006 7:35:07 PM , Rating: 3
quote:
This, folks, you why you should make sure your children stay in school

LOL...sorry, but I just had to point it out. ;)


RE: Intel Talks...
By Questar on 3/12/2006 8:56:37 PM , Rating: 2
LOL, yeah, I guees I need to go back to English class!


Intel does a lot of TALKING but that's about it.
By Beenthere on 3/8/06, Rating: -1
By zsdersw on 3/8/2006 10:00:38 PM , Rating: 2
Anyone who doubted my assertion in another story's comment section that there are idiots here need only look to this guy's comments (Beenthere).


By AMaench7 on 3/8/2006 10:25:27 PM , Rating: 2
Agreed..as it is right now they are about a cycle behind AMD. Their only saving grace as of late was the Intel Core Duo(Yohan), that is the only processor giving AMD a run for their money.

I especially enjoyed the tests Intel ran the other day on their new state of the art system versus a cycle behind AMD. Then claiming it could kick the crap out of AMD and that we should all hail them as pioneers. Wait till AMD launches full DDR2-800 support and puts Intel back in their seat again.


By hans007 on 3/8/2006 11:21:12 PM , Rating: 2
hyperthreading is not a thing just for the netburst architecture.

i am sure it will come back when threading becomes more prevalent. right now, 2 cores are probably ok, as the benefit to going to say 4 logical cpus i dont think intel feels is worth using hyperthreading at this point as most desktop users would not see a difference.

it is different in the server space, as the power5 and sparc chips all have some form of hyperthreading. in reality the company most behind on this type of technology is AMD as it does not appear to be on any of their roadmaps.


as it is, from my understanding in college, hyperthreading would do something like this. say you have an instruction that just does integer addition. if the cpu has say a shifter unit, or say a divide unit , you would then be able to say run 2 instructions if the other one was only going to use the shifter. so it can in certain situations make a huge difference, thus why sun and power5 use it.


By Xenoterranos on 3/9/2006 1:32:37 AM , Rating: 2
But now it's all about economics isn't it. Why are they going to spend the time, money, and die space to re-develop hyperthreading for this architecture when they can just keep heeping on gobs of cache? I mean honestly, 16mb cache? I can't decide if thats a design decision or a bandaid?!


By JackPack on 3/9/2006 2:54:44 AM , Rating: 2
16MB is for Tulsa only.


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