Understanding AMD's "TLB" Processor Bug
December 5, 2007 11:56 AM
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Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake
Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design.
The Tech Report
AMD's iteration of Intel's F00F bug
. The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes.
How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software uses nested memory pages, this processor will experience a race condition.
AMD's desktop product marketing manager Michael Saucier describes a race condition as a series of events "where the other guy wins who isn't supposed to win."
In the software world, a typical memory race condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory to somewhere else in cache. In the instance where two arbiters follow this same rule set, its easy to see how a race condition can occur: both arbiters attempt to overwrite the same blocks of information, resulting in a deadlock.
From what AMD engineers would tell
, this example is very similar to what occurs with nested memory pages in virtualized machines on these K10 processors.
AMD has since released a new BIOS patch for all K10 motherboards, including
the often cited but rarely seen MSI K9A2 Platinum
. This patch, confirmed by
, will result in at least a 10% reduction in general computing speed.
AMD partners tell
that all bulk
shipments have been halted pending application screening based on the customer. Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques. Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime.
The TLB erratum will be fixed in the B3 stepping of all AMD quad-core processors, including Phenom and
. However, AMD considers the B3 stepping a "March" item on its 2008 roadmap. Processors shipped between then and now will still carry the TLB bug, though with the BIOS workaround these machines will not experience a lockup.
The delayed Phenom 9700 is affected by the TLB bug, though AMD insiders tell
the upcoming 2.6 GHz Phenom 9900 is not affected
. This indicates Phenom 9900 will carry the B3-stepping designation.
AMD's latest roadmap hints that its tri-core processors are merely quad-core processors with one core disabled. The company also indicated that it will introduce some of these tri-core processors with the L3 cache disabled. Removing the shared-L3 cache from the chip design eliminates the TLB bug.
In a likely-related event, AMD's newest corporate roadmap scheduled three Phenom processors for the first half of 2008; one of which is the Phenom 9700. The company will launch
eleven new 65nm K8 processors in the same time period
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RE: Not good
12/6/2007 7:53:35 AM
Intel has never been the underdog and they DID take advantage of their lead to rest on their laurels. Nobody weeps for the guy who had everything and lost it due to his own complacency.
I think it's similar but honestly I think AMD tried (and failed). I truly don't believe this was a case of laziness on AMD's part. I could be wrong though.
Intel is the best for a reason. They have the money, the market, and the people to make the best processors and they've got nothing but themselves in their way. AMD has themselves, money, market and everything else in their way. For AMD winning is an up hill battle, it's simply not that way for Intel.
RE: Not good
12/6/2007 11:08:22 AM
I agree with you on priciple, but, really...it sure seems like AMD has gone out of their way to make all sorts of just stupid mistakes.
The ATI acquisition, though a forward-looking and fundamentally sound decision, could not have possibly been more ill-timed. They had a really strong toe-hold on gaining market share at the expense of their biggest competitor and then inexplicably changed a winning game plan. Even with the knowledge that Larrabee is upcoming, they could have waited a few years to ensure that Barcelona would at least keep the market share they had gained, vice ending up in a price war that led to a new round of debt sales. Does anyone really think we would be discussing this L3 errata if all the ATI money had gone into Barcelona R&D?
I also have to wonder how much better ATI discrete cards would have been if that division hadn't been saddled with being the bread-winner in the family.
Why not just buy controlling interest in ATI, and then gradually keep buying more ATI stock until you get to the point that full acquisition doesn't require such a huge one time outlay of cash? That way, they could have had enough influence on ATI's chipset division to ensure that Spider would still become a reality, yet retain enough cash to properly fund K10 development. There was a wide variety of differing paths to take to get ATI, yet they chose the one, that while may have provided instant gratification, was also probably the most myopic.
I sure hope they get their act together. I so miss actually having "choice" when it comes to enthusiast procs. Let's face it, right now, the only difficult decision to make WRT buying a new proc is WHICH Intel fits your price/performace range.
...and this comes from a guy loving his 939 FX-60 (OC'd to 3.0, ;) )
"So if you want to save the planet, feel free to drive your Hummer. Just avoid the drive thru line at McDonalds." -- Michael Asher
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