Understanding AMD's "TLB" Processor Bug
December 5, 2007 11:56 AM
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Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake
Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design.
The Tech Report
AMD's iteration of Intel's F00F bug
. The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes.
How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software uses nested memory pages, this processor will experience a race condition.
AMD's desktop product marketing manager Michael Saucier describes a race condition as a series of events "where the other guy wins who isn't supposed to win."
In the software world, a typical memory race condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory to somewhere else in cache. In the instance where two arbiters follow this same rule set, its easy to see how a race condition can occur: both arbiters attempt to overwrite the same blocks of information, resulting in a deadlock.
From what AMD engineers would tell
, this example is very similar to what occurs with nested memory pages in virtualized machines on these K10 processors.
AMD has since released a new BIOS patch for all K10 motherboards, including
the often cited but rarely seen MSI K9A2 Platinum
. This patch, confirmed by
, will result in at least a 10% reduction in general computing speed.
AMD partners tell
that all bulk
shipments have been halted pending application screening based on the customer. Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques. Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime.
The TLB erratum will be fixed in the B3 stepping of all AMD quad-core processors, including Phenom and
. However, AMD considers the B3 stepping a "March" item on its 2008 roadmap. Processors shipped between then and now will still carry the TLB bug, though with the BIOS workaround these machines will not experience a lockup.
The delayed Phenom 9700 is affected by the TLB bug, though AMD insiders tell
the upcoming 2.6 GHz Phenom 9900 is not affected
. This indicates Phenom 9900 will carry the B3-stepping designation.
AMD's latest roadmap hints that its tri-core processors are merely quad-core processors with one core disabled. The company also indicated that it will introduce some of these tri-core processors with the L3 cache disabled. Removing the shared-L3 cache from the chip design eliminates the TLB bug.
In a likely-related event, AMD's newest corporate roadmap scheduled three Phenom processors for the first half of 2008; one of which is the Phenom 9700. The company will launch
eleven new 65nm K8 processors in the same time period
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RE: testing failures
12/5/2007 7:31:57 PM
AMD is doing their best to spin the Barcelona/Phenom situation as having this "one bad bug".
It is by no means the reality of the situation. The current steppings of Barcelona/Phenom are riddled with bugs: small, medium, and large.
The recent B2 stepping was so bad it was immediately dumped and work begun on a B3 stepping. It is not likely that further steppings will substantially fix the design. The Barcelona is a fabulous prototype design, but it is a long way away from being a polished production level design.
So AMD is going to plan B -- 65nm K8-based chips -- and will wait on volume shipments of K10 until the reworked Barcelona B+ is finished sometime 2H08.
There will some small shipments of K10 chips between now and 2H08, but only the foolish will buy these machines. If you have clout with AMD, insist on a replacement policy.
Overall, K10 is just too much change at the wrong time. Split-plane power is a nice idea, but it obsoletes all existing motherboards. A massive change from K8 is warranted for massive gains, but the gains have been elusive and even when found, merely marginal.
AMD should have used their own technology and built a simple K8+ quad-core that glued together two dual-core processors. All the cores should have been glued together with HT3, giving the processor a massive jump in on-chip bandwidth while protecting backward compatibility. Bump the cache sizes up with a move to 65nm and you have a chip that required almost zero development effort that is ready to ride. A few tweaks to the K8 memory controller to support unbuffered ECC 800Mhz and ECC 1066Mhz DDR2 and you would still have a very competitive processor. On the desktop, the many fast low-latency DDR2 modules could also be supported.
Too bad. Brute force often works better than finesse. This is something that AMD should have learned from Intel by now.
"The Space Elevator will be built about 50 years after everyone stops laughing" -- Sir Arthur C. Clarke
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