Understanding AMD's "TLB" Processor Bug
December 5, 2007 11:56 AM
comment(s) - last by
Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake
Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design.
The Tech Report
AMD's iteration of Intel's F00F bug
. The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes.
How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software uses nested memory pages, this processor will experience a race condition.
AMD's desktop product marketing manager Michael Saucier describes a race condition as a series of events "where the other guy wins who isn't supposed to win."
In the software world, a typical memory race condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory to somewhere else in cache. In the instance where two arbiters follow this same rule set, its easy to see how a race condition can occur: both arbiters attempt to overwrite the same blocks of information, resulting in a deadlock.
From what AMD engineers would tell
, this example is very similar to what occurs with nested memory pages in virtualized machines on these K10 processors.
AMD has since released a new BIOS patch for all K10 motherboards, including
the often cited but rarely seen MSI K9A2 Platinum
. This patch, confirmed by
, will result in at least a 10% reduction in general computing speed.
AMD partners tell
that all bulk
shipments have been halted pending application screening based on the customer. Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques. Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime.
The TLB erratum will be fixed in the B3 stepping of all AMD quad-core processors, including Phenom and
. However, AMD considers the B3 stepping a "March" item on its 2008 roadmap. Processors shipped between then and now will still carry the TLB bug, though with the BIOS workaround these machines will not experience a lockup.
The delayed Phenom 9700 is affected by the TLB bug, though AMD insiders tell
the upcoming 2.6 GHz Phenom 9900 is not affected
. This indicates Phenom 9900 will carry the B3-stepping designation.
AMD's latest roadmap hints that its tri-core processors are merely quad-core processors with one core disabled. The company also indicated that it will introduce some of these tri-core processors with the L3 cache disabled. Removing the shared-L3 cache from the chip design eliminates the TLB bug.
In a likely-related event, AMD's newest corporate roadmap scheduled three Phenom processors for the first half of 2008; one of which is the Phenom 9700. The company will launch
eleven new 65nm K8 processors in the same time period
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RE: Not good
12/5/2007 6:20:15 PM
Yea, on the desktop or workstation end, quad core is nice but not critical. Quad core servers on the other hand offer virtualization on multiple servers without the heavy licensing and hardware costs normally associated with it.
RE: Not good
12/6/2007 4:54:33 AM
Well, was the released Phenoms with the BIOS that made them work 100% albeit somewhat slower or were they with a faulty BIOS that is faster.
If it was fully working they will do better against the Core2 processors but probably a little slower anyway.
RE: Not good
12/6/2007 10:44:25 AM
the BIOS fix will most probably disable the 2 MB L3 cache
"I modded down, down, down, and the flames went higher." -- Sven Olsen
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