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Print 64 comment(s) - last by clnee55.. on Dec 24 at 2:33 AM

Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake

Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design. 

Yesterday, The Tech Report confirmed AMD's iteration of Intel's F00F bug.  The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes. 

How does the TLB erratum occur?  All AMD quad-core processors utilize a shared L3 cache.  In instances where the software uses nested memory pages, this processor will experience a race condition. 

AMD's desktop product marketing manager Michael Saucier describes a race condition as a series of events "where the other guy wins who isn't supposed to win." 

In the software world, a typical memory race condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory to somewhere else in cache.  In the instance where two arbiters follow this same rule set, its easy to see how a race condition can occur: both arbiters attempt to overwrite the same blocks of information, resulting in a deadlock.

From what AMD engineers would tell DailyTech, this example is very similar to what occurs with nested memory pages in virtualized machines on these K10 processors. 

AMD has since released a new BIOS patch for all K10 motherboards, including the often cited but rarely seen MSI K9A2 Platinum.  This patch, confirmed by DailyTech, will result in at least a 10% reduction in general computing speed. 

AMD partners tell DailyTech that all bulk Barcelona shipments have been halted pending application screening based on the customer.  Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques.  Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime. 

The TLB erratum will be fixed in the B3 stepping of all AMD quad-core processors, including Phenom and Barcelona.  However, AMD considers the B3 stepping a "March" item on its 2008 roadmap.  Processors shipped between then and now will still carry the TLB bug, though with the BIOS workaround these machines will not experience a lockup. 

The delayed Phenom 9700 is affected by the TLB bug, though AMD insiders tell DailyTech the upcoming 2.6 GHz Phenom 9900 is not affected.  This indicates Phenom 9900 will carry the B3-stepping designation.

AMD's latest roadmap hints that its tri-core processors are merely quad-core processors with one core disabled. The company also indicated that it will introduce some of these tri-core processors with the L3 cache disabled.  Removing the shared-L3 cache from the chip design eliminates the TLB bug.

In a likely-related event, AMD's newest corporate roadmap scheduled three Phenom processors for the first half of 2008; one of which is the Phenom 9700.  The company will launch eleven new 65nm K8 processors in the same time period.


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RE: Not good
By yost007 on 12/5/2007 5:23:10 PM , Rating: 2
I agree with your point. A "fix" that imparts a 10% penalty is not much of a fix.


RE: Not good
By Clauzii on 12/5/2007 5:51:27 PM , Rating: 2
I would say that "A fully slower but working CPU ALWAYS is better than NO CPU. Think about it ;)


RE: Not good
By kalak on 12/7/2007 1:45:09 PM , Rating: 2
quote:
A fully slower but working CPU ALWAYS is better than NO CPU


Err. NO. Not in this case. A fix that cause another problem ? That's not good. And in the world of CPU competition, 10% less speed is a doom... AMD need a better solution to this (though I think they don't care anymore...)


RE: Not good
By DeepBlue1975 on 12/8/2007 1:54:50 PM , Rating: 2
I'll answer your post with a question:

Why get a CPU that needs a 10% performance cap to work well, when you can go and buy a CPU that works right away with no problem at all, and even has a better price, and more performance out of the box (even when the Phenom is "unfixed"?

Intel didn't even need the penryn to compete in this conditions. Problem is, they are going to find that out really soon and slow their cycles and start making their CPUs more expensive.


RE: Not good
By Master Kenobi (blog) on 12/5/2007 6:17:25 PM , Rating: 2
In the industry this would be classified as a "workaround" since the "problem" still exists and has not yet been corrected.

The Caveat to this "workaround" by AMD, is they are going to get further thrashed in benchmarks.....


"The Space Elevator will be built about 50 years after everyone stops laughing" -- Sir Arthur C. Clarke

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