Print 64 comment(s) - last by clnee55.. on Dec 24 at 2:33 AM

Much of AMD's bad luck over the last three months revolves around a nasty bug it just can't shake

Erratum, to those in the hardware or software industry, is a nice way of saying "we missed a test case" during development and design. 

Yesterday, The Tech Report confirmed AMD's iteration of Intel's F00F bug.  The bug, which has been documented since at least early November, can cause a deadlock during recursive or nested cache writes. 

How does the TLB erratum occur?  All AMD quad-core processors utilize a shared L3 cache.  In instances where the software uses nested memory pages, this processor will experience a race condition. 

AMD's desktop product marketing manager Michael Saucier describes a race condition as a series of events "where the other guy wins who isn't supposed to win." 

In the software world, a typical memory race condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory to somewhere else in cache.  In the instance where two arbiters follow this same rule set, its easy to see how a race condition can occur: both arbiters attempt to overwrite the same blocks of information, resulting in a deadlock.

From what AMD engineers would tell DailyTech, this example is very similar to what occurs with nested memory pages in virtualized machines on these K10 processors. 

AMD has since released a new BIOS patch for all K10 motherboards, including the often cited but rarely seen MSI K9A2 Platinum.  This patch, confirmed by DailyTech, will result in at least a 10% reduction in general computing speed. 

AMD partners tell DailyTech that all bulk Barcelona shipments have been halted pending application screening based on the customer.  Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques.  Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime. 

The TLB erratum will be fixed in the B3 stepping of all AMD quad-core processors, including Phenom and Barcelona.  However, AMD considers the B3 stepping a "March" item on its 2008 roadmap.  Processors shipped between then and now will still carry the TLB bug, though with the BIOS workaround these machines will not experience a lockup. 

The delayed Phenom 9700 is affected by the TLB bug, though AMD insiders tell DailyTech the upcoming 2.6 GHz Phenom 9900 is not affected.  This indicates Phenom 9900 will carry the B3-stepping designation.

AMD's latest roadmap hints that its tri-core processors are merely quad-core processors with one core disabled. The company also indicated that it will introduce some of these tri-core processors with the L3 cache disabled.  Removing the shared-L3 cache from the chip design eliminates the TLB bug.

In a likely-related event, AMD's newest corporate roadmap scheduled three Phenom processors for the first half of 2008; one of which is the Phenom 9700.  The company will launch eleven new 65nm K8 processors in the same time period.

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RE: Not good
By michal1980 on 12/5/2007 1:17:16 PM , Rating: 2
but wont the 'fix' slow down everyones pc? even if they are not using vt?

RE: Not good
By KristopherKubicki on 12/5/2007 1:21:51 PM , Rating: 2
Yes since there are corner cases with nested memory pages outside of virtualization.

RE: Not good
By masher2 on 12/5/2007 2:54:32 PM , Rating: 2
I'm not seeing the benefits of Barcelona's nested paging outside of virtualization. Do you happen to know what those corner cases might be?

RE: Not good
By KristopherKubicki on 12/5/2007 4:16:38 PM , Rating: 2
Well, it wouldn't be the processor that enables nested memory pages -- that's the software. There's nothing that says you can't have memory sitting on top of other memory -- although when we're talking system memory instead of L3 cache that's the potential for a buffer overflow.

I don't pretend to understand exactly how the memory arbiters for K10 work, though knowing the problem affects nested memory and knowing you have multiple cores accessing/writing that L3 cache, it seems like that is a hot spot for race conditions.

RE: Not good
By masher2 on 12/5/2007 4:47:41 PM , Rating: 2
> "Well, it wouldn't be the processor that enables nested memory pages -- that's the software"

By "nested memory pages", I assumed you meant Barcelona's nested paging feature, which I think AMD is now actually calling "Rapid Virtualization Indexing". Am I wrong on this?

RE: Not good
By KristopherKubicki on 12/5/2007 4:56:23 PM , Rating: 2
I was not directly referring to AMD's technology. My colleagues at Tech Report just published the Linux patch notes that detail what went wrong. It's not too different from the general example I used:

RE: Not good
By wetwareinterface on 12/6/2007 4:35:02 AM , Rating: 2
sql database
certain multithreaded apps that rely on cpu to cpu cache lookups and use nested paging to achieve this without specifically addressing either l1 l2 or l3 cache memory addresses but use instead placeholder locations and let the cpu/compiler try to decide where the cache address is. i.e. most c++ only optimized for multithreading not address lookup stability compiler code written using the c language default of pointers instead of actual memory location addressing. basically any half assed custom written in c++ app that you may find in a corporate enviornment like most individual crm client server based products.


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