AMD Resurrects K8 Architecture for 2008 Roadmap
Kristopher Kubicki & Gabriel Ikram
December 5, 2007 10:22 AM
comment(s) - last by
AMD plans to keep "Brisbane" around, releases new chips based on it
Things at AMD may have gone from bad to worse with the lackluster Phenom launch in late November. Not only did Phenom fail to appeal to professional reviewers, but the company ended up removing
one third of its CPU lineup just after the big day
Last week AMD CEO Hector Ruiz vowed that the company would stop hemorrhaging cash and return to profitability soon. "That is our number one goal right now," Ruiz said
in a conference in Bangalore
Making a profit at AMD apparently means refocusing on its older K8 architecture. The company will introduce eleven 65nm K8 processors over the next two quarters. By comparison: AMD launched two quad-core K10 Phenom processors in November
with three more scheduled over the next two quarters
. Two tri-core Phenom processors
will follow in March 2008
Essentially, AMD will move any remaining Athlon 64 processors from the 90nm node to the 65nm node, with a few new frequency and TDP variations.
The AMD Athlon 64 X2 5600+ will be the first to jump on the new 65nm K8 bandwagon with a 65W TDP.
of the same featured an 89-Watt TDP. AMD will also add 100 MHz to the core frequency of the Athlon 64 X2 5600+, now rated at 2.9 GHz. Total L2 cache will be halved in the move to the Brisbane core, and the updated Athlon 64 X2 5600+ chips will feature only 1MB of L2 cache. Availability of these processors is scheduled for Q1 2008.
AMD's higher-end Athlon 64 X2 6400+ and Athlon 64 X2 6000+ will both be discontinued.
AMD will also update its "Energy Efficient" series and will release three new chips, the AMD Athlon 4850e, Athlon 4450e, and Athlon 4050e in Q2 2008. All of the new offerings will be based on AMD's
core and will feature a 45-Watt thermal envelope. AMD's current energy efficient "BE-2xxx" series will be phased out at that time. Respectively, the new chips will run at 2.5GHz, 2.3GHz and 2.1GHz.
chips will be based on the Socket AM2 interface. These processors are compatible with AMD's AM2+ socket designated for Phenom processors.
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RE: Goodbye AMD
12/5/2007 1:15:21 PM
Yes, they could try to do something very creative, or, simply copy Intel's design. It doesn't seem to matter much where the memory controller is placed judging from the performance of Conroe. At least, we don't hear much about the superiority of the IMC since Conroe debuted. That bullet has pretty much been shutdown. AMD must do something to get back in the game. K10 is not going well at all. That L3 cache design flaw is really absurd. They totally dropped the ball on that one. It seems everything hinges on K10 right now. If they can keep K8 going then they can relax and work on getting K10 right.
RE: Goodbye AMD
12/5/2007 5:50:47 PM
Yes and No. Conroe gets away with kicking butt and having the Controller on the North Bridge because Intel's engineers worked some magic. AMD's IMC and HT bus can feed their processor faster than Intel can (Theoretically). Intel compensates for this by increasing the L2 cache into the 2-12MB range and using extremely slick algorithms to do intelligent pre-fetching. Allowing it to feed data into the chip at a rate the chip can use without a performance hit where the CPU is idling on cycles because it can't get information quickly enough.
To go with Intel's north bridge method, AMD would not only have to come up with a better prefetch method, but also increase the L2 and possibly L3 (Jury is still out on how effective L3 cache really is, Barcelona/Phenom was not the best of implementations based on the theories I've read about) into the megabyte range much as Intel has.
With Intel's move to Nehalem, they will be sporting the Native Quad Core design much like Barceona/Phenom, they will also be sporting the Integraged Memory Controller, and the new Intel QuickPath (Faster and more bandwidth than Hyper-Transport 3.0 supposedly). Now Intel is also adding Hyper-Threading back in so it will show up as 8 Processors to Windows (Should be pretty slick). If Intel can find a way to glue 2 of those together and not have the memory controllers fighting, AMD could copy that (If they haven't figured out how to do it by then). Right now they would have to re-engineer their chips and chipsets to a point that would make them both incompatable with current boards and chipsets, as well as force them to redesign the CPU's and a lot of the logic built into it that is based around being linked to the IMC. Sounds like too much cost and headache to get around it. Best bet would be to develop a way to not have the IMC's fight with each other.
In Summary.... Intel played their cards right and played their strengths and milked every last bit out of the North Bridge, Legacy BUS, and their processes. They were able to take a cheap route based on existing architecture and glue two dice together and make out like bandits.
AMD Ran with new tech like IMC, and Hyper-Transport and while it has worked well for them (K7/K8) it seems to have closed that door for them, up until such time as they can figure out how to get 2 IMC's to play nicely. That's really the only thing stopping them from doing exactly what Intel is doing.
RE: Goodbye AMD
12/7/2007 2:37:30 AM
Well done.... the argument boils down to cache really.
Fast bus + small cache or slow bus + large cache, the design choice of either combination is balanced to hit certain performance goals.
Cache hit/miss rate goes as a power law in terms of overall capability, the larger the cache the lower the miss rate (a miss being a situation where the processor needs data but does not find it in cache).
Small caches have high miss rates, to mitigate the penalty for going to DRAM, simply design a bus to get it there faster (high BW, low latency), so if you miss say 5 times out of 20 attempts, you may pay only 8 cycles penalty waiting.
Large caches have low miss rates, so you may only miss 2 times out of 20, but you must pay 12 cycles penalty waiting on the slow bus.... just an example.
It is completely possible with the 'archaic' FSB to out perform the novel and slick IMC implementation so long as the caching technology is par excellent (which C2D has), consequently high quality memory is not nearly as impactive on a well cached CPU as opposed to a cache lean CPU.
Where the FSB becomes more problematic are in large throughput, large working set situations where even a larger cache becomes overwhelmed ... hence SPECFP_rates (large data sets, high through put) really shine on the high BW busses.
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