AMD Tri-core Processor Details for 2008 and 2009
December 4, 2007 2:56 AM
comment(s) - last by
AMD has something for everyone with its new tri-core processors, but quite a lot is still marked "tentative"
AMD picked up big headlines
the day before Intel's Fall Developer Forum
with the announcement of its upcoming tri-core processors.
AMD's original release did not specify if this tri-core processor, code named
, would be a totally new processor or merely a stripped-down version of
. The answer, it appears, is both.
In an embargoed corporate roadmap forwarded to
, details of these new triple-core oddities came to light.
The first triple-core processor,
, is essentially a core-disabled version of the
quad-core processor. It includes a full
package, including the 2MB of shared L3 cache, with one core disabled.
, which will eventually herald the AMD Phenom 8000-product name, is scheduled to launch in February 2008 with mass availability in March. AMD representatives, speaking on conditions of anonymity, confirmed the initial 2.4 GHz Phenom 8700 and 2.3 GHz Phenom 8600 tri-core processors will launch with a 95W thermal envelope.
In late 2008, AMD will shift almost all of its 65nm quad-core offerings to 45nm. AMD will then follow up these initial quad-core offerings with 45nm dual-core and triple-core processors in 2009.
The first of these 45nm tri-core processors, codenamed
, will launch with DDR2 and DDR3 support. However, AMD guidance also details that
will ship with two different varieties: one with a shared L3 cache, another without. All 45nm quad-core AMD processors incorporate shared L3 cache, with
the exception of the
AMD guidance goes on to state that all mainstream Phenom quad-core processors, both with shared L3 cache (
) and without (
), shipped in 2009 will feature DDR3 exclusively.
, on the other hand, will feature a mix of DDR2 and DDR3 support.
Unfortunately the answers for tri-core only raise further questions. While
has a unique codename, it seems to be a combination of cut-down
quad-core processors. The logical conclusion would be that
is merely excess or defective
processors from the 2008 launch.
Yet AMD's roadmap goes on to detail one more chip:
which has always been described by AMD as a dual-core version of
, will make its debut with variable shared L3 cache and a mix of DDR2 and DDR3 support. Could it be that
is a core-disabled version of
, which is already likely a core-disabled version of
One AMD representative declined to comment on these 45nm processors, stating that 2009 processor launches and specifications are still "tentitive."
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RE: Three cores?
12/4/2007 9:07:17 AM
actually the celeron 300a was nowhere near a pentiumII with cache disabled. the pentium II had the l2 cache running at half the cpu frequency because it was external to the die. it was 4 way set assosciative also. the celeron cache was internal to the die, ran at cpu frequency, and was 8 way set assosciative. it was a precursor to the pentium III "coppermine". the coppermine upped the cache ante by going 16 way set assosciative and having 4 times as much cache as the celeron 300a. the 300a also had 2 cache areas, one was always disabled to improve yields. it looked like the 300a was going to be the pentium III but intel decided to go a different route and reuse the pII manufacturing process to extend the life of the process and make more money off it. later they redid the pIII as the coppermine and just basically bumped up the celey specs to the coppermine ones.
RE: Three cores?
12/4/2007 9:46:42 AM
The Precursor to the Coppermine was the Katmai, not the Pentium 2 Destchue
And the early Celerons had no Cache.
"Young lady, in this house we obey the laws of thermodynamics!" -- Homer Simpson
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