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The test chips Rambus will use in its demonstration  (Source: Rambus Inc.)
Rambus plans to deliver huge leap in memory bandwidth by 2011

Rambus Inc. plans to announce this Wednesday a new memory signaling technology initiative targeted at delivering a Terabyte-per-second of memory bandwidth, which the company touts as a solution for next-generation multi-core, game and graphics applications.

Rather than simply increasing the clock speed of memory to achieve higher output, Rambus looks to boost bandwidth with a 32X data rate. Just as DDR memory technologies doubles transfer on a single, full clock signal cycle, Rambus’ proposed technology is able to data at 32 times the reference clock frequency. With 32X technology, the memory company is targeting a bandwidth of 16Gbps per DQ link with memory running at 500MHz. In contrast, today’s DDR3 at 500MHz achieves a bandwidth of 1Gbps.

“We're really excited about the Terabyte Bandwidth Initiative and the technologies that we've developed,” said Steven Woo, a senior principle engineer at Rambus. “The work of a large team of our scientists and engineers is pushing memory signaling technology to new levels of performance.”

Of course, it requires a little explanation on how a technology that enables a DQ link 16Gbps of bandwidth could result in a Terabyte of throughput. Rambus’ aim for the technology is to grant Terabyte bandwidth to a system on a chip (SoC) architecture, and such may be achieved with 16 DRAMs operating at 16Gbps, 4-bytes wide per device.

Another innovation that Rambus plans to integrate into its Terabyte memory initiative is FlexLink C/A (command/address), which the company claims is the industry’s first full-speed, scalable, point-to-point C/A link – with the C/A running at full speed along with the DQ. FlexLink C/A also simplifies the interface between the memory controller and DRAM. For example, traditional legacy interfaces may require a 12 wire interface, FlexLink C/A can operate point-to-point with just two wires.

Furthermore, FlexLink C/A is named for its flexibility given to system designers, as now the overhead wires freed from the FlexLink C/A interfaces may be devoted to more data wires. Conversely, the model may offer greater bandwidth with the addition of more FlexLink C/A wires, making the technology more easily scalable.

Rambus’ Terabyte bandwidth initiative will use a fully differential memory architecture, which will employ differential signaling for both the C/A and DQ. While current DDR3 and GDDR5 memory use differential signaling for data and strobe, Rambus aims for full differential at the DQ and C/A. Advantages of going full differential include better signal integrity, especially due to its suitability for use in low-voltage electronics, such as memory.

While this Terabyte bandwidth memory method isn’t slated for market until 2011, Rambus has recently received early silicon capable of demonstrating its technology. The early test rig uses emulated DRAM chips, connected to a Rambus memory controller at a 32X data rate capable of 64Gbps. Rambus will show its silicon test vehicle this Wednesday at the Rambus Developer Forum in Tokyo, Japan.



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RE: Wondering...
By ChronoReverse on 11/26/2007 12:22:36 PM , Rating: 2
It's interesting. The advent of PCI-E (full duplex channels to the video card) and DX10 in Vista was supposed to allow for that since it (gpu memory) was supposed to be fully virtualized and available.

Somewhere along the way, things broke down (Nvidia decided they didn't want to implement that) and it was moved out of DX10. I believe that DX10.1 has this again (but of course DX10.1 "doesn't matter").


RE: Wondering...
By scrapsma54 on 11/26/2007 5:28:41 PM , Rating: 1
Cpu's are more about number crunching, not Input. However, dual core computers allow for better synthesis such as Low Data input but High data output. They are more vulnerable to latency. Intel Core 2 Dup Processors remedy this and allow larger chunks of data to be processed in few clocks as possible. GPU's are not vulnerable to latency because GPU's can take each channel and process information In huge chunks, and latency is not important because the human eye won't notice these changes in latency. CPU's are more for Physics and ai, however less demanding on memory resources, are demanding on cpu resources. Ever gamed on single core computer and you will notice that on games Like Gears of War where the physics parameters are decoupled from the Frame rate, the frame rate of the object is slow while the game runs as normal. Dual core relieves the timing involved so the cores don't have to wait for information to pass through to move on.


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