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The test chips Rambus will use in its demonstration  (Source: Rambus Inc.)
Rambus plans to deliver huge leap in memory bandwidth by 2011

Rambus Inc. plans to announce this Wednesday a new memory signaling technology initiative targeted at delivering a Terabyte-per-second of memory bandwidth, which the company touts as a solution for next-generation multi-core, game and graphics applications.

Rather than simply increasing the clock speed of memory to achieve higher output, Rambus looks to boost bandwidth with a 32X data rate. Just as DDR memory technologies doubles transfer on a single, full clock signal cycle, Rambus’ proposed technology is able to data at 32 times the reference clock frequency. With 32X technology, the memory company is targeting a bandwidth of 16Gbps per DQ link with memory running at 500MHz. In contrast, today’s DDR3 at 500MHz achieves a bandwidth of 1Gbps.

“We're really excited about the Terabyte Bandwidth Initiative and the technologies that we've developed,” said Steven Woo, a senior principle engineer at Rambus. “The work of a large team of our scientists and engineers is pushing memory signaling technology to new levels of performance.”

Of course, it requires a little explanation on how a technology that enables a DQ link 16Gbps of bandwidth could result in a Terabyte of throughput. Rambus’ aim for the technology is to grant Terabyte bandwidth to a system on a chip (SoC) architecture, and such may be achieved with 16 DRAMs operating at 16Gbps, 4-bytes wide per device.

Another innovation that Rambus plans to integrate into its Terabyte memory initiative is FlexLink C/A (command/address), which the company claims is the industry’s first full-speed, scalable, point-to-point C/A link – with the C/A running at full speed along with the DQ. FlexLink C/A also simplifies the interface between the memory controller and DRAM. For example, traditional legacy interfaces may require a 12 wire interface, FlexLink C/A can operate point-to-point with just two wires.

Furthermore, FlexLink C/A is named for its flexibility given to system designers, as now the overhead wires freed from the FlexLink C/A interfaces may be devoted to more data wires. Conversely, the model may offer greater bandwidth with the addition of more FlexLink C/A wires, making the technology more easily scalable.

Rambus’ Terabyte bandwidth initiative will use a fully differential memory architecture, which will employ differential signaling for both the C/A and DQ. While current DDR3 and GDDR5 memory use differential signaling for data and strobe, Rambus aims for full differential at the DQ and C/A. Advantages of going full differential include better signal integrity, especially due to its suitability for use in low-voltage electronics, such as memory.

While this Terabyte bandwidth memory method isn’t slated for market until 2011, Rambus has recently received early silicon capable of demonstrating its technology. The early test rig uses emulated DRAM chips, connected to a Rambus memory controller at a 32X data rate capable of 64Gbps. Rambus will show its silicon test vehicle this Wednesday at the Rambus Developer Forum in Tokyo, Japan.

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RE: Wondering...
By DeepBlue1975 on 11/26/2007 12:08:31 PM , Rating: 5
Graphics processors are massively parallel, and can benefit from a stupidly high bandwidth.
And, also, they process a lot of multi megabyte images every second, so they also need to move data very fast.

CPUs, on the other hand, are not so parallel and normal PC applications are not designed to make heavy use of multi threading.

Thus, in GPUs, every time you overclock the memory frequency, in the higher resolutions / anti aliased modes you get a noticeable improvement, while in CPUs, to get any kind of benefit from a higher bandwidth, you have to overclock the CPU's clock through the roof to take advantage of it.

Just think that every time Intel or AMD released a chip of the same family and frequency, but with different FSB / HTT link speed, at stock speeds you couldn't notice any performance gain, not even using super expensive, ultra high bandwidth ram.

On the other hand, CPU usage patterns generally dictate that they have to fetch small quantities of data, very often. And in those situations lower latency helps. But bandwidth does not.

RE: Wondering...
By drank12quartsstrohsbeer on 11/26/2007 2:10:25 PM , Rating: 2
Are you suggesting that increasing the system memory's speed does not improve performance?

RE: Wondering...
By DigitalFreak on 11/26/2007 3:24:15 PM , Rating: 4
For the most part, yes. Read some of the articles on Anandtech regarding upgrades to the C2D FSB, for example.

RE: Wondering...
By drank12quartsstrohsbeer on 11/26/2007 5:38:10 PM , Rating: 4
groovy. I still have some 30 pin simms laying around. time to put them to work.

RE: Wondering...
By DeepBlue1975 on 11/29/2007 8:16:21 AM , Rating: 2
Yep, it's like the diminishing returns theory.

You can find lots of articles through CPU history, when some chip maker launched a new CPU from the same family and frequency than another existing model, but sporting one single difference: faster FSB Speed (or, for what matters, official support for faster memory modules when using a 1:1 ratio for mem / FSB).

The performance is always virtually the same. At least at stock speeds, when overclocking things can change a bit, though... But just a bit, you can usually gain somewhere from 1 - 5% in performance when using a heavily overclocked CPU if you also overclock memory speed.

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