Rambus Inc. plans to announce this Wednesday a new memory signaling
technology initiative targeted at delivering a Terabyte-per-second of memory
bandwidth, which the company touts as a solution for next-generation
multi-core, game and graphics applications.
Rather than simply increasing the clock speed of memory to
achieve higher output, Rambus looks to boost bandwidth with a 32X data rate.
Just as DDR memory technologies doubles transfer on a single, full clock signal
cycle, Rambus’ proposed technology is able to data at 32 times the reference
clock frequency. With 32X technology, the memory company is targeting a
bandwidth of 16Gbps per DQ link with memory running at 500MHz. In contrast,
today’s DDR3 at 500MHz achieves a bandwidth of 1Gbps.
“We're really excited about the Terabyte Bandwidth Initiative
and the technologies that we've developed,” said Steven Woo, a senior principle
engineer at Rambus. “The work of a large team of our scientists and
engineers is pushing memory signaling technology to new levels of performance.”
Of course, it requires a little explanation on how a
technology that enables a DQ link 16Gbps of bandwidth could result in a Terabyte
of throughput. Rambus’ aim for the technology is to grant Terabyte bandwidth to
a system on a chip (SoC) architecture, and such may be achieved with 16 DRAMs
operating at 16Gbps, 4-bytes wide per device.
Another innovation that Rambus plans to integrate into its
Terabyte memory initiative is FlexLink C/A (command/address), which the company
claims is the industry’s first full-speed, scalable, point-to-point C/A link –
with the C/A running at full speed along with the DQ. FlexLink C/A also
simplifies the interface between the memory controller and DRAM. For example,
traditional legacy interfaces may require a 12 wire interface, FlexLink C/A can
operate point-to-point with just two wires.
Furthermore, FlexLink C/A is named for its flexibility given
to system designers, as now the overhead wires freed from the FlexLink C/A
interfaces may be devoted to more data wires. Conversely, the model may offer
greater bandwidth with the addition of more FlexLink C/A wires, making the
technology more easily scalable.
Rambus’ Terabyte bandwidth initiative will use a fully
differential memory architecture, which will employ differential signaling for
both the C/A and DQ. While current DDR3 and GDDR5 memory use differential signaling
for data and strobe, Rambus aims for full differential at the DQ and C/A.
Advantages of going full differential include better signal integrity,
especially due to its suitability for use in low-voltage electronics, such as
memory.
While this Terabyte bandwidth memory method isn’t slated for
market until 2011, Rambus has recently received early silicon capable of
demonstrating its technology. The early test rig uses emulated DRAM chips,
connected to a Rambus memory controller at a 32X data rate capable of 64Gbps.
Rambus will show its silicon test vehicle this Wednesday at the Rambus
Developer Forum in Tokyo, Japan.
