AMD "Spider" Crawls Up the Water Spout
November 18, 2007 3:16 AM
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AMD guidance details the backwards and forwards compatibility of the AM2, AM2+ and AM3 sockets.
AMD details its platform progression identically to Intel's "tick-tock" architecture roadmap.
AMD announces its Spider Platform in what could be its biggest launch of all time
Tomorrow marks the launch of AMD's platform launch, codenamed
. The launch consists of three components: AMD Phenom processors, the ATI Radeon HD 3800 graphics processor and AMD 7-Series desktop chipsets.
The first new AMD desktop architecture in four years will debut with the Phenom 9500 and Phenom 9600. Both chips feature a 95-Watt thermal envelope and a shared 2MB L3 cache.
The AMD Phenom 9600 ships with a 2.3GHz operating frequency, while the Phenom 9500 features a slightly lower 2.2GHz clock. Both processors run on HyperTransport 3.0 and feature a total 2MB L2 cache; 512KB per core. The chips also come with an integrated DDR2 memory controller and support speeds up to the DDR2-1066 specification, which is still pending JEDEC approval.
the Phenom 9600 at a retail price of $322.00 and the Phenom 9500
that a 2.4GHz Phenom, dubbed the Phenom 9700, would also launch on November 19, however last minute roadmap updates indicate this chip will come in December instead.
These two Phenom processors are part of AMD's first-generation, 65nm
. In the second-half of 2008 AMD will announce its
, which will be a migration of the current K10 core to the 45nm node.
lineup consists of five variants, including quad-core
. The second-generation
CPUs will also include an
integrated DDR3 memory controller
, a first for AMD.
AMD's Spider Platform launch also includes the official announcement of its ATI Radeon HD 3800 Series. The launch of the Spider platform will add two new video cards to AMD's lineup, the ATI Radeon HD 3870 and Radeon HD 3850.
new Radeon series
received overwhelmingly positive feedback during AMD's November 15 media event. Newegg representatives tell
the company sold out all of its stock on the first day, but is quickly replenishing inventory.
To round off the launch of the platform, AMD also announced its 7-Series desktop chipsets. The AMD 790FX targets the ultra-enthusiast market segment, and corporate guidance sets the retail price of 790FX boards between $150-250. Several partners already announced boards
supporting this new chipset earlier this year
AMD designates the AMD 790X as its performance chipset, slotted just below the 790FX. AMD guidance states this chipset will run the consumer between $99-150. The mainstream AMD 770 chipset will not see store shelves for several months, but AMD claims this chip will round off the mainstream segment for AMD chipsets.
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RE: AMD continues to disappoint
11/19/2007 8:16:04 AM
simply being 'true-native' quad core provides no distinct advantage.
It never did. "Native" anything has been subjective at best. In theory it should eliminate cross talk bottle necks between the cores because they will use the interconnect rather than HT or Bus. While it will do this, the real world gain is so far not apparent. With Intel switching to QuikPath and Native Quads with Nehalem in the July/August '08 time frame this will be a moot point shortly anyways. By the way, Hyper-Threaded native quad cores for Nehalem.... 8 execution paths? Intel is a beast :)
I have a theory that sandwitching 2 together might cause problems for the memory controller (obviously you would get 2 and one has to be disabled). But I'm starting to wonder if they use native designs simply because it would cause some cross talk depending on which side the working memory controller was on.. Intel's MC is still on the north bridge so it could sling data to the processor without much trouble, just a logic update to which side to send it to. Maybe I'm just talking out my ass here but it was just a random thought that jumped into my head while reviewing the native/non-native quad designs.
RE: AMD continues to disappoint
11/19/2007 3:24:06 PM
Well done, well explained -- yes... AMD's share L3 cache eliminates the cache coherency problem at the L3 level, but they are discrete at L1/L2, the native design makes the coherency snooping much faster. The MCM that snoop goes across the FSB, no doubt ... however, the penalty is obviously small and in raw performance, well, we see the results.
I can dig up the link, but I have seen a few reference that the normal coherency pattern is that most snoops (80 or 90%) result in a NAK, which means the MCM is not paying the penalty 90% of the time...
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