Print 46 comment(s) - last by NullSubroutine.. on Mar 2 at 6:04 PM

New retention mechanism

1207 pins
AMD's new LGA-1207 is ready for quad-core Opterons

Although at this time, details are scarce, we are able to reveal some images of AMD's next-generation Opteron socket, called Socket F. AMD's Socket F will be a LGA-type socket with 1207 pins, and is an entirely new design from current Opteron sockets. We've read that the new socket will be used for upcoming dual-core Opterons as well as quad-core Opterons. The new socket comes with an updated retention mechanism.

Intel adopted the LGA socket design with Prescott to reduce cost and also to reduce the defect rate on processors.  After all, would you rather scrap a $600 CPU for a bent pin, or a $100 motherboard for a bent land grid?  A few days ago, we got some pictures of the upcoming Intel 771 LGA socket for Xeon motherboards.

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RE: Great News
By defter on 2/24/2006 5:11:45 PM , Rating: 3
You make a very valid and understandable point. However, the spec is nearly finalized and it would not be hard for AMD to build in unofficial support for such a thing just like they did with DDR500 support in the Athlon64s and Intel did with HT in the old P4s.

The difference is that support for DDR500 was just a support for different memory dividers. DDR3 chip spec isn't finished and AFAIK spec for DDR3 modules is far from being finished. Thus AMD simply cannot make currently DDR3 controller that is 100% guaranteed to work with DDR3 modules that will be released in 2007/2008.

Similar to ATi's and nVidia's memory controllers on their respective GPUs.

ATi and nVidia don't have memory controllers that support three completely different standards. Supporting GDDR1/2/3 is quite easy, GDDR2 is backwards compatible and GDDR3 is just a slight modification, all these memory technologies are parallel in nature, have same bus width, etc..

What you are proposing is that AMD will support serial, narrow (16bit?) and fast (clocked at several GHzs) memory technology (FB-DIMM, XDR) and parallel, wide (128bit) and slow (clocked below 1GHz) memory technology (DDR2, DDR3) with the same memory controller. This is just impossible. They would need to implement different memory controllers, reserve different pins to them etc. And besides, why would you use XDR on Socket-F? It definately isn't designed for server use.

Here is specifically what I was referring to

Here is what I was referring to:

"AMD Chooses Direct Rambus Interface Technology for Processor Chipsets

--First Test Chips Are Already Functional at Full Speed--

SUNNYVALE, CA -- October 8, 1998 --AMD announced today it has licensed the Direct Rambus™ high-bandwidth memory interface for use in forthcoming logic chips, and that the technology will be the main memory interface for future personal computer products. Test chips for the company's initial program are functional at full-speed, 800 MHz operation."

How many AMD's RDRAM chipsets made to the shops?

"Spreading the rumors, it's very easy because the people who write about Apple want that story, and you can claim its credible because you spoke to someone at Apple." -- Investment guru Jim Cramer
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