Intel Slates "Nehalem" for Q4 2008
October 26, 2007 10:58 AM
comment(s) - last by
New sockets, chipsets and architecture en route from Intel before 2009
will likely be the most aggressive processor architecture in Intel's portfolio since the original Pentium. With the launch of the Core architecture, the company announced its tick-tock strategy: design new architecture, then shrink the process node. Rinse and repeat.
Tick-tock is alive and well as Intel's corporate roadmap reveals additional details about its desktop iteration of 45nm quad-core
will be fundamentally different from the Core architecture for no less than two reasons. The company will move the memory controller from the core logic on the motherboard to the processor die. This tactic has been a cornerstone for the AMD K8 architecture since 2003.
will also feature a new bus interconnect,
currently dubbed Quick Path Interconnect
. This new interconnect behaves very similar to HyperTransport, currently used on all AMD platforms since K8.
A new bus and memory controller means a new socket design. Existing motherboards are not compatible with
-based processors. The new desktop socket, labeled LGA1366, will completely replace the existing LGA775 interconnect.
The company will replace the X38 and
yet to be announced X48 desktop chipsets
chipset family and ICH10 southbridge for these first LGA1366 motherboards.
Corporate guidance also suggests the company will likely ditch all DDR2 support in favor of DDR3, at least on the high end platforms. All
processors will feature support three DDR3 channels.
However, not everything is known about
just yet. Corporate guidance suggests
will feature a new revision of Hyper-Threading. Although each
features four physical cores, the processor will dynamically allocate additional threads --
computers will detect eight logical cores.
will feature less cache than Intel's high-end 45nm
offerings slated for release between now and Q4 2008. However, unlike the 12MB L2 cache featured on
, the 8MB L3 cache on all
offerings can be shared between all four on-die cores.
processors will feature a 130W thermal envelope. Extreme Edition
processors, the first on the 45nm node, have a thermal envelope that tops out around 136W. Intel's Q9550 processor (2.8 GHz, 45nm quad-core) sports a 95W TDP.
Paul Otellini, Intel CEO,
boldly announced that
as "taped out" at the Intel Developer Forum last September
. The tape out designates when a design team has moved from the design to working samples.
At both Intel and AMD, the tape out comes approximately one year before the actual launch date. True to tick-tock,
's debut will also come
one year after the 45nm node launch
This article is over a month old, voting and posting comments is disabled
RE: What I'd like to see.
10/29/2007 9:57:03 AM
As far as I know AMD does not hold the patent for HyperTranport, just as Intel does not hold the patent for PCI (and variants).
Using a motherboard memory controller and disabling the on die controller would not be impossible with a BIOS update. A CPU can detect the Chipset it's installed on and enable or disable it. Just like you can enable and disable hyperthreading, XD Bit, CPU serial number, and other CPU features etc.
RE: What I'd like to see.
10/29/2007 10:00:27 AM
What I meant was, AMD included in their design was to allow for reverse compatibility with older DDR designs. Anandtech has the article on the topic. I think it was DDR3 maintaining reverse compatibility with DDR2.
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