Print 78 comment(s) - last by Martimus.. on Nov 21 at 2:05 PM

New sockets, chipsets and architecture en route from Intel before 2009

Nehalem will likely be the most aggressive processor architecture in Intel's portfolio since the original Pentium. With the launch of the Core architecture, the company announced its tick-tock strategy: design new architecture, then shrink the process node.  Rinse and repeat.

Tick-tock is alive and well as Intel's corporate roadmap reveals additional details about its desktop iteration of 45nm quad-core Nehalem, dubbed Bloomfield.

Nehalem will be fundamentally different from the Core architecture for no less than two reasons. The company will move the memory controller from the core logic on the motherboard to the processor die.  This tactic has been a cornerstone for the AMD K8 architecture since 2003.

In addition, Nehalem will also feature a new bus interconnect, currently dubbed Quick Path Interconnect.  This new interconnect behaves very similar to HyperTransport, currently used on all AMD platforms since K8.

A new bus and memory controller means a new socket design. Existing motherboards are not compatible with Nehalem-based processors.  The new desktop socket, labeled LGA1366, will completely replace the existing LGA775 interconnect. 

The company will replace the X38 and yet to be announced X48 desktop chipsets with the Tylersburg chipset family and ICH10 southbridge for these first LGA1366 motherboards. 

Corporate guidance also suggests the company will likely ditch all DDR2 support in favor of DDR3, at least on the high end platforms.  All Bloomfield processors will feature support three DDR3 channels.

However, not everything is known about Nehalem just yet.  Corporate guidance suggests Bloomfield will feature a new revision of Hyper-Threading.  Although each Bloomfield features four physical cores, the processor will dynamically allocate additional threads -- Bloomfield computers will detect eight logical cores.

Bloomfield will feature less cache than Intel's high-end 45nm Penryn offerings slated for release between now and Q4 2008.  However, unlike the 12MB L2 cache featured on Penryn, the 8MB L3 cache on all Nehalem offerings can be shared between all four on-die cores.

Intel's highest-end Bloomfield processors will feature a 130W thermal envelope.  Extreme Edition Penryn processors, the first on the 45nm node, have a thermal envelope that tops out around 136W.  Intel's Q9550 processor (2.8 GHz, 45nm quad-core) sports a 95W TDP.

Paul Otellini, Intel CEO, boldly announced that Nehalem as "taped out" at the Intel Developer Forum last September.  The tape out designates when a design team has moved from the design to working samples. 

At both Intel and AMD, the tape out comes approximately one year before the actual launch date.  True to tick-tock, Bloomfield's debut will also come one year after the 45nm node launch, or Penryn.

Comments     Threshold

This article is over a month old, voting and posting comments is disabled

RE: What I'd like to see.
By TLCKurovski on 10/27/2007 7:19:37 PM , Rating: 2
I like the fact that they have integrated the FSB on to the CPU but I'd rather see Intel keep the socket LGA775 platform and disable the on die memory controller
That would be very, very difficult. They would need to make compatible layouts for the sockets, they would need to include a mux for the two interfaces, they would need to keep a FSB interface and they would need to comunicate this interface to the XBar.
when it's used on with DDR2 or motherboard that has a northbridge memory controller installed.
And how would it know what was the kind of MB?
I'd also like to see Intel ditch the "not invented here" syndrome and adopt an existing proven industry supported Hypertransport protocol.
Go to Sunnyvale and try to license ccHT :)...

Of course, CSI is far from being a HT clone. Intel has different requirements, they should have different PtP interconnects.
Also, It would be nice if they took the AMD approach to on die FSB and allow backward computability with older memory technology, thus allowing users and oems to use the type of RAM most suitable for their budget or application.
This is difficult to do. And almost useless.

RE: What I'd like to see.
By Googer on 10/29/2007 9:57:03 AM , Rating: 2
As far as I know AMD does not hold the patent for HyperTranport, just as Intel does not hold the patent for PCI (and variants).

Using a motherboard memory controller and disabling the on die controller would not be impossible with a BIOS update. A CPU can detect the Chipset it's installed on and enable or disable it. Just like you can enable and disable hyperthreading, XD Bit, CPU serial number, and other CPU features etc.

RE: What I'd like to see.
By Googer on 10/29/2007 10:00:27 AM , Rating: 2
What I meant was, AMD included in their design was to allow for reverse compatibility with older DDR designs. Anandtech has the article on the topic. I think it was DDR3 maintaining reverse compatibility with DDR2.

"I want people to see my movies in the best formats possible. For [Paramount] to deny people who have Blu-ray sucks!" -- Movie Director Michael Bay
Related Articles
Intel X48, P45, G45 Turn Corporeal
October 26, 2007, 10:45 AM
Intel Preps 45nm Quad-core Desktop Launch
September 28, 2007, 4:44 AM
"Nehalem" Taped-out and Running Windows
September 18, 2007, 12:04 PM

Copyright 2016 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki