The Death of Moore's Law: T-Minus 15 Years and Counting
Michael Hoffman & Kristopher Kubicki
September 19, 2007 11:46 AM
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A young Gordon Moore circa 1975
Gordon Moore took part in the afternoon keynote during IDF 2007
The fall edition of the 2007 Intel Developer Forum (IDF) is officially underway from the San Francisco Moscone Center. The Tuesday morning keynote featured more
details about the
as one of the main points of the discussion.
In a later session, Dr. Moira Gunn, host of NPR Tech Nation, hosted a fireside chat with Gordon Moore, Intel co-founder and creator of Moore's Law. Moore received a well-deserved standing ovation from the crowded conference hall packed with thousands of attendees more than willing to respect a Silicon Valley legend.
Of course, the question on everyone's mind was the validity of Moore's Law. Specifically, whether or not it holds up today the same way it did when Moore first documented his observations almost forty years ago.
Moore's Law -- actually more of a conjecture -- essentially states the number of transistors placed on an integrated circuit doubles every two years. His observation helped outline trends the semiconductor industry for more than 40 years.
"We have another decade, a decade and a half, before we hit something that is fairly fundamental," Moore said during the session. That something "fundamental" is material science. Even the most advanced lithography conceivable today can't eliminate the brick wall that is the nanoscale.
Even at some point, lining up individual atoms no longer becomes feasible for transistor design. Researchers from Intel are already easing into the field of using carbon nanotubes for processor interconnects; a team from
the University of Pennsylvania just announced a new method for storing data
via phase-changing nanowires
"It's an exciting time," he said. "I'd love to come back in 100 years and see what happened in the meantime."
Of course, even Moore's understanding of transistor trends is no match for the prowess of ambitious engineers. Conventional computing principles go out the window with
the advent of quantum computing
, for example. Other types of alternative computing, including biological-based neural-computing, does not readily translate to transistor-count -- but that hasn't stopped researchers from
making enormous progress in the last few years
The death of Moore's Law is imminent, but new research and new materials assure that its successor will pack the same punch.
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RE: Already dead
9/20/2007 11:52:11 PM
Well, not really ... The node, as defined fixes the pitch between the first two metal lines of the first metallization layer. ITRS defines the process node in their roadmap:
page 6 has a nice diagram and the definition above..
People often think that the litho node refers to the smallest feature size on the transistor, this is not true. The smallest feature size that must be patterend is the Lg, (*distance between source and drain, making up the channel*) and depending on design, will be roughly 1/2 to 1/3 of the distance 1/2 Pitch at M1 -- at least that is the trend I have noted.
So at 65 nm, roughly 30 nm or so... in fact, both AMD and Intel have published 35 nm gate lengths at the 65 nm node, so that range is close. The TCAD, which designs the transistor has to make the gate to gate pitch commensurate with the M1 to M1 metal line pitch, otherwise, you would not be able to wire up the transistor. Going from your description, say left edge of the gate to the same gate edge on the adjacent transistor defines the total area taken by the transistor (source, channel, drain) plus the isolation between... the total pitch relative to M1 (as two adjacent M1 lines span a souce and a gate, sould then be 2xnodex2 roughly, so at 65 nm, for example, 2 x 65 x 2 give 260 nm of space to build the transistor and isolate it, at 45 nm this goes down to 180 nm.
The key to CADing out the transistor is maximize the overall drive current at the lowest leakage. Now, you mention stress ... good. Because in the absense of classical scaling, Intel and AMD turned to stress engineering to increase mobility as opposed to using geometry to drive up drive currents. This works good at 90 nm, not as well at 65 nm and will yield diminishing returns the smaller you go.... it is not stress that is actually phenomena, it is strain which is induced by stress. Stress is a pressure, strain though is a force... pressure is force/unit area... so if I stress over say area A1 and in my next revision stress over area A2 such that A2 < A1, then the induces strain is significantly less in the shrink.
Interestingly, AMD employed 2 major stressors in their 90 nm process (dual stress liners), but going to 65 nm the effectiveness of this stressing technique diminished enough that they obviously tried to put in two more (embedded SiGe and stress memorization), and even then they are struggling to recover and hit 90 nm speed bins... so it is tough, but it can be done even at 65 nm dimensions.
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