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New Phenom triple-core processor coming in 2008

AMD today updated its roadmap with another multi-core processor, to slot between its dual and quad-core processors – Phenom triple-core processors. The new Phenom triple-core processors feature three processing cores on a single die and based on AMD’s Barcelona architecture, which launched last week in Opteron form.

The new triple-core processors will feature similar specifications as its upcoming Phenom X2 and X4 brethren. The Socket AM2+ processors feature 512KB of L2 cache for each core and a shared pool of L3 cache. Essentially, the Phenom triple-core processors are quad-core variants with one core disabled. This allows AMD to simply disable one core on quad-core dies for maximum use of a single wafer.

AMD claims to be the only company to offer tri-core processors, which the company claims to bring “true multi-core technology to a broader audience.” AMD has not given the Phenom triple-core processors an official name yet. However, it wouldn’t be too surprising if the tri-core processors followed the current Phenon naming scheme and received the Phenom X3 name.

“With our advanced multi-core architecture, AMD is in a unique position to enable a wider range of premium desktop solutions, providing a smarter choice for customers and end users,” said Greg White, vice president and general manager, Desktop Division, AMD. “As a customer-centric company, AMD is committed to working with our OEMs to deliver compelling value propositions across their multi-core product families with capabilities that address their requirements and aspirations.”

Features unique to AMD’s Barcelona and Stars architectures such as split power planes and dynamic independent core speed adjustments remain supported on triple-core processors. Additionally, AMD Phenom triple-core processors support HyperTransport 3.0 for up to 16GB/second of I/O bandwidth.

AMD claims significant performance gains over dual-core processors with its triple-core processors in benchmarks such as SYSmark 2007 and 3DMark06, where gaming and digital content creation performance is key.

“A continued commitment to elegant design and innovative processor architecture is instrumental to revolutionizing the technology industry,” said Richard Shim, research manager for IDC's Personal Computing program. “The advent of triple-core processors is a valuable market opportunity for customers to deliver end users compelling solutions and further differentiate on the desktop.”

Expect AMD to launch its Phenom triple-core processors in Q1 2008. AMD plans to launch its quad-core Phenom X4 next quarter.

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RE: What market segment is this aimed at?
By jak3676 on 9/18/2007 12:23:50 AM , Rating: 2
in terms of "current architecture", the split power plane is only a split between the memory controller and the cores - it is not a split between the cores.

from Anand Tech's article

AMD has made numerous improvements compared to the K8 core:
The FPU unit can be turned off when not needed
Clock gating is implemented much better
Each core can run at its own frequency (but the voltage is the highest needed by either core)
Power for the core and memory controller are split

I do agree that there would be some power savings here, but we're not talking about disabling 1/4 of the chip. With ~ 460 million transistors for the entire CPU, the number of non-cache transistors in the Barcelona core is ~250 million total or ~62 million per core. So disabling one core cuts out just over 13% of the total transistors.

RE: What market segment is this aimed at?
By jak3676 on 9/18/2007 2:06:44 PM , Rating: 4
I don't really mind getting rated up or down for my usual rambling - but can someone explain why this post got rated down? This is straigt fact and numbers. If I quoted a number wrong, please let us all know.

By deeznuts on 9/18/2007 11:08:17 PM , Rating: 2
Fanboys, just ignore it. They sometimes act irrationally, so asking or thinking about it rationally isn't going to get you anywhere.

By mars777 on 9/19/2007 3:23:16 PM , Rating: 3
Maybe because individual cores can already save power and clock by themselves with cool&quiet.
This is only made to clock differently the IMC thus saving power when it's not 100% loaded with memory requests.

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