Quick and Dirty Quad-Core "Penryn" Benchmarks
Chris Ram & Anh T. Huynh
August 23, 2007 10:46 PM
comment(s) - last by
CPU ID screen shot of "Yorkfield" at 2.33 GHz
Intel "Yorkfield" ScienceMark 2 L2 cache performance
DailyTech managed to snag a quad-core "Yorkfield" for a few quick benchmarks
Benchmarks of Intel’s
appeared a couple times
in the past month. The early benchmarks tested engineering sample processors and showed
, on average, performing 5 percent faster, clock for clock then
. However, benchmarks of the quad-core
are virtually non-existent to the public.
is not a native quad-core design. As with
features two dual-core dies fused together. The design results in each pair of cores having access to its own pool of shared L2 cache. Since
has more cache, each pair of cores has access to 6MB of L2 for a total of 12MB – up from the 4MB per pair and 8MB total of
In addition to the increased cache size,
a faster 24-way associative L2 cache
, which cuts off a few clock cycles.
has an 16-way associative L2 cache.
also features new SSE4 instructions catered towards multimedia tasks. SSE4 introduces 47 new instructions to improve performance of video accelerators, graphics building blocks and streaming load. Intel claims a 2x performance gain in video acceleration tasks. There are 14 new instructions for video accelerator performance enhancement. Intel improves compiler auto-vectorization performance with 32 new instructions.
Intel expects SSE4 optimizations to deliver performance improvements in video authoring, imaging, graphics, video search, off-chip accelerators, gaming and physics applications. Early benchmarks with an SSE4 optimized version of DivX 6.6 Alpha yielded a
116 percent performance improvement
due to SSE4 optimizations.
Also new to
is the Super Shuffle Engine. Intel’s Super Shuffle Engine allows for shuffling unpacking, packing, align concatenated sources, wide shifts, insertion and extraction, and setup for horizontal arithmetic functions. Intel claims a “2x faster SSE shuffle instruction execution,” according to earlier briefing documents.
Although Yorkfield uses a 45nm fab process and consumes less power, Intel plans to stick to its existing 95 Watt and 130 Watt thermal design power ratings.
previously presented quick and dirty benchmarks of
AMD’s 1.6 GHz
processor last June. Today,
has a few quick and dirty benchmarks of Intel’s quad-core
Core 2 processor, in an LGA775 package.
The testing configuration is as follows:
Intel Core 2 Extreme QX6700 @ 2.33 GHz, 1333 MHz front-side bus
2.33 GHz, 1333 MHz front-side bus
Intel P35 Express based motherboard
2x1GB DDR3-1333 memory
AMD ATI Radeon HD 2600 XT
Since Intel does not have a 2.33 GHz
processor, a Core 2 Extreme QX6700 is used. The Core 2 Extreme QX6700 has an unlocked multiplier, which allowed us to clock it at 2.33 GHz with a 1333 MHz front-side bus.
SiSoft Sandra XII CPU-Arithmetic
SiSoft Sandra XII CPU Multimedia
SiSoft Sandra XII Memory Bandwidth
Synthetic benchmarks do not really reveal too much of a performance difference between
. However, SiSoft Sandra XII does not contain SSE4 optimizations yet.
Unlike AMD, Intel relies on an off-chip memory controller. Although AMD achieves low latencies with its integrated memory controller, Intel manages the same feat with a northbridge-installed controller. Intel managed to offset the latencies associated with off-die memory controllers with increased L2 cache.
additional L2 cache and speedier 24-way associative L2 cache yields an approximate memory bandwidth boost of 7 percent.
Cinebench 10 Performance
Cinebench 10 yields an approximate 8 percent boost in single and multithreaded rendering. Encoding a video file into DivX also yields a similar 8 percent performance boost.
Overall, with our limited time with
, performance of the quad-core processor is roughly 8 percent faster clock for clock than
. However, this is expected as
is essentially a 45nm die shrink of
with a few tweaks here and there.
Expect Intel to begin shipping
in mass quantities in Q1 2008. Quad-core Xeon X5400
processors, which are somewhat similar to
ship in November
This article is over a month old, voting and posting comments is disabled
RE: dies not dice
8/25/2007 1:43:11 AM
Thanks johnsonx, you kicked some serious ass!!!
"We are going to continue to work with them to make sure they understand the reality of the Internet. A lot of these people don't have Ph.Ds, and they don't have a degree in computer science." -- RIM co-CEO Michael Lazaridis
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