DailyTech - Intel Sets "Penryn" Launch Date

Submit News

Hardware Intel Sets "Penryn" Launch Date
Anh Tuan Huynh (Blog) - August 14, 2007 6:18 PM

73 comment(s) - last by Targon.. on Aug 24 at 5:26 AM

Intel prepares boxed quad-core "Penryn" based Xeon processors for November 11

Intel has set the launch date for its Penryn based quad-core Xeon processor family. The company intends to launch seven new Harpertown based models ranging from 2.0-to-3.16 GHz on November 11, according to a posting on Intel’s reseller webpage. Standard “E” bin and performance “X” bin processors launch on November 11.

Intel Xeon processors carrying the “E” designation feature 80-watt TDP ratings while the “X” bin processors have higher 120-watt TDP ratings. Intel does not plan to launch the low-power “L” models until Q1’08, with two models in the pipeline.

Strangely, Intel never issued a formal announcement for the launch of Penryn nor has the November 11 date showed up on roadmaps. Instead, the launch date popped up on a public webpage for resellers.

Penryn Quad-Core Xeon DP
Model	Core Frequency	TDP	L2 Cache	Launch Price
X5460	3.16 GHz	120W	12MB	$1,172
E5450	3.00 GHz	80W	12MB	$851
E5440	2.83 GHz	80W	12MB	$690
E5430	2.66 GHz	80W	12MB	$455
E5420	2.50 GHz	80W	12MB	$316
E5410	2.33 GHz	80W	12MB	$256
E5405	2.00 GHz	80W	12MB	$209

Pricing for Penryn-based Intel Xeon processors begin at $209 for the entry-level E5405 to $1,172 for the top-end X5460. Although Intel set the launch dates for quad-core Xeon based Penryn processors, the company remains silent on the launch date of the desktop and mobile counterparts.

Intel’s Penryn architecture is the next evolution of the Core 2 micro architecture that made its debut with Woodcrest and Conroe processors. Penryn introduces a 45nm fabrication process with a few additional performance enhancements. Most notably, Penryn introduces new SSE4 instructions for enhanced multimedia performance.

Comments

Threshold

Username
Password
remember me

This article is over a month old, voting and posting comments is disabled

RE: overboard

By Jason Clark on 8/14/2007 6:34:39 PM , Rating: 2

When you are bound by your front side bus, you want to stay as far away from memory as you can... thus larger cache.

Parent

RE: overboard

By Anonymous Freak on 8/14/2007 7:16:11 PM , Rating: 1

Yes indeed. I can't wait for CSI to come out and alleviate some of the FSB issues. At least they are finally putting each socket on its own bus. (Yeah, it was in mid '06, but it was a long time coming.)

Parent

RE: overboard

By Targon on 8/15/2007 7:57:37 AM , Rating: 2

That is pretty much what I said in my post that was knocked down to a 0. Without an integrated memory controller, to keep the CPU happy, Intel processors NEED the huge caches we are seeing here. The Integrated memory controller that AMD uses improves the access to memory by such a large amount that a huge cache size isn't needed(though cache is still faster and will improve performance).

Parent

"Well, there may be a reason why they call them 'Mac' trucks! Windows machines will not be trucks." -- Microsoft CEO Steve Ballmer