ATI's Dave Orton Resigns
Anh Tuan Huynh
July 10, 2007 2:31 PM
comment(s) - last by
Former ATI president and CEO resigns from AMD
AMD today announced Dave Orton, executive vice president of AMD,
. The resignation is effective in the end of July 2007. Orton was the former president and chief executive officer of ATI before the
merger with AMD
. A new executive vice president has not been appointed yet.
“It is with mixed feelings that I am leaving AMD,” Orton said. “I am very optimistic about AMD’s future. I believe strongly in the strategies that brought AMD and ATI together and the talented employees of the ‘new AMD’ who are committed to winning in the market by delivering the best possible solutions for customers.”
Orton was one of the “key drivers in the successful integration of AMD and ATI,” according to AMD President and Chief Operating Officer Dirk Meyer. “With his integration work complete and the successful launch of key graphics and chipset products earlier this year, the time was right for Dave to take his personal and professional life in a different direction,” he added.
Despite the “successful integration” of AMD and ATI, the company continues to hemorrhage cash, with
debts mounting up fast
and an estimated $1.1 billion in the bank. The company also posted a
first quarter loss
of $611 million USD.
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7/11/2007 2:36:17 AM
You forgot that scaling isn't linear and dual core Phenom with L3 cache will have about >60% of the Barcelona's die size.
For 65nm, die sizes are about following:
4MB L2 Conroe: 143mm^2
2MB L2 Allendale: 112mm^2
2x512KB L2 Brisbane?: 125mm^2
7/11/2007 5:25:26 PM
No, i was not taking linear approaches. I was taking as measure, factores taken from real implementations(penrym), not the hipotectycal ideal conditions... so the site implies. Nevertheless the error margin should be much less than 10%.
7/11/2007 6:48:45 PM
Good point. So the numbers are
At the 65nm process.
4MB L2 Conroe: 143mm^2
3MB L2/L3 Phenom: ((283/2)+11,2) = 152,7mm2 =>(11,2mm2/MB for L3)
2MB L2 Allendale: (143-(2x12,4) = 118,2mm2 =>(12,4mm2/MB for L2)
1Mb L2 Runa: ((283/2)-(11,2x2) = 119,1mm2
Yes here AMD will have to compete on performance. But since the Barcelona implementation is so cache starved, IMO, we can expect that that 1Mb additional L3 makes a lot of difference from a linear extrapolation, and Phenom X2 will be able to easily compete with Conroe, but with Penryn that will be another story unless clocks go much higher. Can Runa compete with Allendale in performance? we'll have to wait and see the benchs but my idea is yes but no with the 45nm equivalent.
I've scrap Brisbane because according to his roadmap
there is a hole and nevertheless it will only be for 45W or 38W parts centered around barbone and HTPC where GPU/video codec acceleration is more important.
Strange that their 45nm seems to have a much better theoretical scalability. How complicated tradeoffs they had to have done between cache, clock and functions, and how that stall them.
Bottom line is that they have a better design than core 2, perhaps even better than the Penryn enhanced one. How they execute and how it scales its the big difference.
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