AMD Cancels "Lima"
Anh Tuan Huynh
July 2, 2007 5:07 PM
comment(s) - last by
AMD kills "Lima," leaving "Sparta" to succeed "Manila" and "Orleans"
AMD roadmaps reveal the company recently cancelled its single-core
, the 65nm Athlon 64 refresh. AMD began shipping Lima inventory earlier this year, however, the company since removed the codename from its roadmap. “65nm Lima Athlon 64 single-core models have been removed from the roadmap and EOL on several Orleans models has been modified,” the AMD roadmap states.
This leaves AMD with existing
-based processors to carry the Athlon 64 brand. After
models is EOL, there will be no more single-core Athlon 64 branded processors. Instead, AMD will position entry-level dual-core
processors based on
in the low end.
AMD will continue to ship single-core processors. However, all single-core processors will carry the Sempron brand. With
out of the picture,
will be the next new single-core AMD processor. AMD expects to launch
in September 2007 in 256KB and 128KB L2 configurations.
arrives as a replacement for
-core processors and is essentially a 65nm die-shrink of
-based successor arrives in 1H’2008 in the form of
introduces a larger 512KB L2 and HT3 on a Socket AM2+ platform to the Sempron lineup. Succeeding
, which shrinks the fabrication process to 45nm and adds DDR3 memory support.
place beginning in September.
This article is over a month old, voting and posting comments is disabled
Thats what they say now...
7/3/2007 12:11:22 AM
When the next architecture generation start stacking up loads of chips with one one good core, we'll see single-core action again. The prospects are interesting though: What if these single-core chips still had working cache on all three levels? Sure three executable cores would be cut-off from working, but if the cache was still viable- what kind of performance would a single-core chip see from 512kb L2 and, say, 2mb L3?
Even more interesting would be if you could plop two of these into a socket 1207 board. Dual-core, but comprised of two separate super-cores! You'd have a system running with (given, they are physically independent of one another) 1mb L2, and 4mb L3 for only two cores!
"The Space Elevator will be built about 50 years after everyone stops laughing" -- Sir Arthur C. Clarke
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