Intel Unveils Core 2 Duo E6750 Performance
Anh Tuan Huynh
June 25, 2007 8:38 AM
comment(s) - last by
Performance NDA of the upcoming 1333 MHz front-side bus Core 2 Duo E6750 lifted
Intel today lifted the performance non-disclosure agreement, or NDA, for the first product of its
Core 2 Duo E6x50-sequence lineup
—the Core 2 Duo E6750. Despite being the first refreshed Conroe-based processor since the
, the Core 2 Duo E6750 clocks in below the dual-core flagship Core 2 Extreme X6800. Intel clocks the Core 2 Duo E6750 at 2.66 GHz, identical to the E6700.
New to the Core 2 Duo E6750 however, is a faster 1333 MHz front-side bus to match the new
, including the new
. Besides the faster front-side bus, the new Core 2 Duo E6750 has an identical feature set to the E6700 including 4MB of shared L2 cache. Other
Core 2 Duo E6x50-sequence
processors have the same shared 4MB L2 cache configuration and Intel has no plans of releasing a 1333 MHz front-side bus processor with 2MB of L2 cache.
Intel Core 2 Duo
Intel Virtualization, Enhanced Intel SpeedStep, Intel 64 and Execute Disable Bit technologies make a return on the Core 2 Duo E6750 and E6x50-sequence processors.
Intel Trusted Execution Technology
, formerly known as
, sneaks its way into the new Core 2 Duo E6750 and E6x50-sequence processors.
Expect a hard launch of the Core 2 Duo E6750 and E6x50-sequence processors in the coming weeks. Intel plans to launch four Core 2 Duo E6x50-sequence processors with speeds varying from 2.33 GHz to 3.0 GHz including a TXT-less E6540.
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FSB impact on quad core
6/25/2007 10:07:12 PM
It would be more interesting to see the impact of increased FSB performance on a quad core Intel CPU, because the FSB is more likely to be the bottle-neck there: twice as many cores means more demand for memory access across the bus, plus there is extra traffic on the bus with the two dual-core dies communicating with each other.
"I modded down, down, down, and the flames went higher." -- Sven Olsen
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