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Intel says Itanium will continue to sail for the long run

Intel this week revealed new details about where it plans to take its server processor business, specifically with the Itanium processor. As many know, Intel took a gamble on the Itanium when it was released several years ago. Intel's use of a then uncommon Explicitly Parallel Instruction Computing (EPIC) architecture left the majority of the industry unsure of Itanium's practicality in an x86-dominated world. Today however, the Itanium family brings in roughly $3.5 billion per annun for Intel.

Diane Bryant, vice president of Intel's enterprise group, revealed several details that indicate Intel will push forward with Itanium development for the foreseeable future.

Currently, Intel's flagship Itanium 2 processor is the Montecito core. Intel announced Montecito last July, marking the company's first dual-core enterprise and mainframe processor. Until now, Montecito ran on a 533MHz front-side bus but will soon make the transition a 667MHz front-side bus processor in Q4 2007, dubbed Montvale. According to Bryant, Montvale will consist of minor updates, improving bus speed but also improving overall stability.

Recent Intel roadmaps indicate that Montvale will consist of roughly 25 percent of Intel's Itanium business in Q4 2007. By Q1 2008, Intel guidance suggests Montvale will take up a whopping 40 percent of all Itanium 2 sales. Despite Intel's desktop processors currently seeing day light at 65nm, Itanium 2 processors will still be on 90nm manufacturing technology. Montvale will also top out at a core speed of 1.66GHz with a total of 24MB of L3 cache.

Intel's next major milestone in the Itanium family will come with the arrival of Tukwila, a quad-core processor due sometime in late 2008. According to Bryant, Tukwila will be roughly twice as fast as Montecito and feature an on-die memory controller.

This will be a turning point for Intel because with Tukwila's need for a discrete memory controller gone, the company will introduce its long waited common system interface (CSI). Tukwila's use of CSI will be a direct response to AMD's HyperTransport technology. Intel previously stated it will not restrict CSI to the Itanium family, but will eventually use the technology as the main transport bus for the Xeon family as well.

will also come with even larger caches and a new reliability feature called double device data correction (DDDC). DDDC acts as a failsafe mechanism to protect system memory failures from bringing down a live system. In a hardware failure where a memory chip on a memory module fails, DDDC will be able to mark that chip as unusable without compromising system stability. DDDC differs from traditional ECC and parity technology due to its capability to withstand more than one chip failure.

Bryant went on to reveal details about the future release of an entirely new Itanium architecture code-named Poulson. With Poulson, Bryant claims Intel will introduce even more cores; greater scalability and the introduction of 32nm die fabrication for its enterprise segment. The company will skip 45nm technology altogether for Itanium. Bryant did not give details on a possible release date for Poulson although Intel is expecting to introduce 32nm processors in approximately two years.

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By borowki on 6/18/2007 9:04:04 AM , Rating: 2
Is it correct to classify Itanium's VLIW architecture as RISC?

By RamarC on 6/18/07, Rating: -1
By masher2 on 6/18/2007 10:08:27 AM , Rating: 4
Risky, only for those people who mistakenly believed Itanium was intended to supplant Intel's desktop and small-server cpus. Itanium was a glove thrown down to challenge big iron...and in that marketplace, its actually done quite well.

As to the terms themselves, some people have called VLIW an "extension" of superscalar RISC, but in my opinion, there's very little real overlap.

By Laitainion on 6/18/2007 10:36:03 AM , Rating: 2
Origionaly, it was eventually.

From wikipedia (

"During development, Intel, HP, and industry analysts were predicting that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications."

By masher2 on 6/18/2007 11:03:11 AM , Rating: 2
> "During development..."

Those statements were back before Itanium was even named as such, much less released. The target market changed as development proceeded. From the point the design was finalized, Itanium was intended only for the big-iron marketplace.

Long-term though, I wouldn't be surprised if some of those predictions don't ultimately come true. IA-64 benefits from a large cache much more than x64 does. Past the 32nm node, I wouldn't be surprised to find Itanium in low-end servers and some workstations.

By shady28 on 6/18/2007 1:03:33 PM , Rating: 5
Intel's major Itanium vendor is HP. Most of HP's midrange and high end servers will ultimately be itanium only - HP has stopped developing the PA-RISC architecture that has carried them through 20+ years of servers. Seeing HP has about 24% of the server market, that's a good thing for Intel.

Having said that, on a technical basis the Itanium isn't all that great. IBM's Power5 / Power6 is a superior performer, now hitting 4Ghz on a quad core chip and both Power5 and Power6 hold top slots in Spec benchmarking.

By eilersr on 6/18/2007 1:04:41 PM , Rating: 6
No, Itanium's VLIW is a different category than RISC.
VLIW is the name for a the general approach. Intel's approach in Itanium is EPIC (Explicitly Parallel Instruction Computing), which takes VLIW in a slightly different direction.

Don't take these as absolute definitions, but this is how I see it:

RISC: Simple instructions that are easy to process. Most RISC architectures have a relatively small set of well defined instructions (hence, Reduced Inst. Set). Typically every instruction has the same fixed length (# of bits). Greater # of instructions required to accomplish the same operation than CISC, but are typically executed faster than CISC to make up for it.

CISC: Complex instructions that may take longer to process, but accomplish more work per instruction than RISC. Each instruction can have variable bit length, depending on what needs to be done. CISC architectures tend to have many broadly defined instructions for very specific tasks (e.g., all the various SSE instructions). Most modern CISC archictures (incl. x86) break CISC instructions down to something closer to internal RISC-like operations (e.g. micro-ops) to take advantage of architectural techniques that are easier to employ in a RISC architecture (pipelining, super-scalar, etc.)

VLIW: Can think of it as a number of RISC-like instructions that are strung together to achieve a larger operation. The final instructions are much longer than what is seen in CISC architectures. The compiler must do a lot of work to group the sub-instructions together efficiently.

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