Quick and Dirty AMD K10 Cinebench
June 6, 2007 5:12 AM
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Cinebench ran AMD "Barcelona" 1.6 GHz in 27 seconds. (Source: DailyTech, Anh Huynh)
Cinebench ran Xeon X3220 2.4 GHz in 17 seconds. (Source: DailyTech, Anh Huynh)
An early AMD "Barcelona" revision gets its first non-simulated benchmark
Earlier today, AMD announced that it
across the server market. The company did not publically state how fast the processor was running, the stepping of the processor, the processor thermal envelope or the eventual ship date.
We had the opportunity to benchmark the AMD
, native quad-core on an early stepping. We only had a few minutes to test the chip, but we were able to run a quick Cinebench before we were instructed to leave.
The AMD benchmark ran on a single-socket, K10 CPU running at 1.6 GHz on NVIDIA's nForce Professional 3400 chipset. According to the system properties, the AMD system used 4GB of DDR2-667.
The most similar Intel system we could muster up on such short notice was an Intel Xeon 3220. The Xeon X3220 is clocked at 2.4 GHz, and ran on
(Intel X38). This system property profile stated the system utilized 4GB of DDR2-800.
Cinebench completed the default benchmark in 27 seconds for the 1.6 GHz K10; 17 seconds for the Intel Xeon X3220. The
Xeon was 58% faster with a 50% higher clock frequency for Cinebench.
Both systems ran Windows 2003 R2, 64-bit.
AMD partner engineers tell
the chip we tested was the latest revision silicon. The same engineers claim 2.0 GHz
chips are making the rounds, with 2.3 GHz already on the desktop and server roadmaps.
AMD's current guidance suggests a late July announcement for
. However, when
tracked down the individual partners named in AMD's press release, all cited "optimistic September" ship dates for motherboards.
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RE: These chips could be in debug mode...
6/14/2007 1:05:16 AM
I was trying to be careful because I don't know exactly how this works on AMD CPUs, but what I meant was that in the CPUS I worked with (back in the day) there are a bunch of configuration bits that got clocked into the chip at startup to control its function. I believe that the same thing happens with modern x86 chips except that these bits come from the BIOS.
When we were debugging MIPS chips and new multiprocessor system architectures, we sometimes needed to change those configuration bits to tell the chip not to use certain performance features because they would cause the chip to produce incorrect results.
For example, if the chip was having trouble with cache coherent loads using an update protocol, we would switch the chip into invalidate mode - slower in some situations, but it worked. Or when the chips were new, we would have to make sure that the sysad bus (MIPS equivalent to FSB) ran at a particular fraction of the internal clock. Or we would have to disable out-of-order execution...
It's actually a lot like software debugging. It's all about testing as much logic as you can. You have to find as many bugs as you can before you spin the chip so sometimes you have to have to run at significantly lower performance just to get the OS to boot and run benchmarks properly. Then you fix a whole bunch of bugs and critical paths at the same time and respin the chip.
We don't know where AMD is in that process, but you'd have to hope that these chips are early silicon that was able to run correctly but had performance features turned off or not well tuned (what I soemwhat simplisticly referred to as "debug mode"). It's possible that the chips are being respun as we type.
If anyone would like to enlighten me on how AMD chips get configuration bits from the BIOS and what they control (do they still load microcode?), let me know!
"If you mod me down, I will become more insightful than you can possibly imagine." -- Slashdot
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