IBM is taking a cue from nature to build the next generation of
computer chips. IBM borrowed the natural pattern-creating process that
forms seashells, snowflakes and tooth enamel to help create next-generation
chips. The method forms trillions of holes to create vacuums as insulation
around the miles of nano-scale wires packed next to each other inside the chip.
Today, chips are manufactured with copper wiring surrounded
by an insulator, which involves using a mask to create circuit patterns by
beaming light through the mask and later chemically removing the parts that are
The new technique skips the masking and light-etching
process, opting to use a vacuum gap – misleadingly referred to as airgaps – as
an insulator. IBM scientists discovered the right mix of compounds, which they
poured onto a silicon wafer with the wired chip patterns, and then baked.
This concept occurs in nature for the formation of snowflakes,
seashells and tooth enamel. The major difference is that IBM has been able to
direct the self-assembly process to form trillions of holes that are all
similar, while the processes that occur in nature are all unique.
This process provides the right environment for the
compounds to assemble in a directed manner, creating trillions of uniform,
nano-scale holes across an entire 300 millimeter wafer. These holes are just 20
nanometers in diameter, up to five times smaller than would be possible using
today’s most advanced lithography technique.
Once the holes are formed, the carbon silicate glass is
removed, creating a vacuum between the wires allowing the electrical signals to
either flow 35 percent faster, or to consume 15 percent less energy. A vacuum
is believed to be the ultimate insulator for what is known as wiring
capacitance, which occurs when two conductors, in this case adjacent wires on a
chip, sap or siphon electrical energy from one another, generating undesirable
heat and slowing the speed at which data can move through a chip.
“This is the first
time anyone has proven the ability to synthesize mass quantities of these
self-assembled polymers and integrate them into an existing manufacturing
process with great yield results,” said Dan Edelstein, chief scientist of the
self-assembly airgap project. “By moving self assembly from the lab to the fab,
we are able to make chips that are smaller, faster and consume less power than
existing materials and design architectures allow.”
IBM boasts that its self-assembly nanotechnology process provide
the equivalent of two generations of Moore's Law wiring performance improvements
in a single step. The self-assembly process already has been integrated with
IBM manufacturing line in East Fishkill, New York and is expected to be fully
incorporated in IBM’s manufacturing lines and used in chips in 2009. Furthermore,
this new technology can be incorporated into any standard CMOS manufacturing
line, without disruption or new tooling.
The chips will be used in IBM's server product lines and
thereafter for chips IBM builds for other companies, for example, the Cell
Broadband Engine found in the PlayStation 3 and various servers.
Over the past few months, IBM has had a number of major chip
technology announcements and demonstrations that the company claims will extend
Moore’s Law. In December, IBM announced the first 45nm chips using immersion lithography
and ultra-low-K interconnect dielectrics.
In January, IBM announced high-k metal gate,
which substitutes a new material into a critical portion of the transistor that
controls its primary on/off switching function. In February, IBM revealed its
on-chip memory technology that features the fastest access times
ever recorded in eDRAM. Then in March, IBM unveiled a prototype optical
transceiver chipset capable of reaching speeds at least eight-times faster
than optical components available today. More recently, IBM developed a new chip stacking technology that shortens wire lengths inside chips up to 1000 times.