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This microprocessor cross section shows vacuums in between the chip's wiring that serve as insulators between each wire
IBM chip production takes cue from snowflakes, seashells and from your teeth

IBM is taking a cue from nature to build the next generation of computer chips. IBM borrowed the natural pattern-creating process that forms seashells, snowflakes and tooth enamel to help create next-generation chips. The method forms trillions of holes to create vacuums as insulation around the miles of nano-scale wires packed next to each other inside the chip.

Today, chips are manufactured with copper wiring surrounded by an insulator, which involves using a mask to create circuit patterns by beaming light through the mask and later chemically removing the parts that are not needed.

The new technique skips the masking and light-etching process, opting to use a vacuum gap – misleadingly referred to as airgaps – as an insulator. IBM scientists discovered the right mix of compounds, which they poured onto a silicon wafer with the wired chip patterns, and then baked.

This concept occurs in nature for the formation of snowflakes, seashells and tooth enamel. The major difference is that IBM has been able to direct the self-assembly process to form trillions of holes that are all similar, while the processes that occur in nature are all unique.

This process provides the right environment for the compounds to assemble in a directed manner, creating trillions of uniform, nano-scale holes across an entire 300 millimeter wafer. These holes are just 20 nanometers in diameter, up to five times smaller than would be possible using today’s most advanced lithography technique.

Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires allowing the electrical signals to either flow 35 percent faster, or to consume 15 percent less energy. A vacuum is believed to be the ultimate insulator for what is known as wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, sap or siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip.

 “This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results,” said Dan Edelstein, chief scientist of the self-assembly airgap project. “By moving self assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow.”

IBM boasts that its self-assembly nanotechnology process provide the equivalent of two generations of Moore's Law wiring performance improvements in a single step. The self-assembly process already has been integrated with IBM manufacturing line in East Fishkill, New York and is expected to be fully incorporated in IBM’s manufacturing lines and used in chips in 2009. Furthermore, this new technology can be incorporated into any standard CMOS manufacturing line, without disruption or new tooling.

The chips will be used in IBM's server product lines and thereafter for chips IBM builds for other companies, for example, the Cell Broadband Engine found in the PlayStation 3 and various servers.

Over the past few months, IBM has had a number of major chip technology announcements and demonstrations that the company claims will extend Moore’s Law. In December, IBM announced the first 45nm chips using immersion lithography and ultra-low-K interconnect dielectrics.

In January, IBM announced high-k metal gate, which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. In February, IBM revealed its on-chip memory technology that features the fastest access times ever recorded in eDRAM. Then in March, IBM unveiled a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today. More recently, IBM developed a new chip stacking technology that shortens wire lengths inside chips up to 1000 times.



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Busy IBM, more like BS from IBM.
By ChipDude on 5/4/2007 8:39:28 PM , Rating: 2
It burns me up that the press and idiot tech wanna pretenders think there is something here.

Talk about a company so desperate to return to glory. IBM microelectronics is now a small and irrelevant piece of IBMs business. But once they were king, inventor of the DRAM, leader of scaling, leader in BJT performance, publisher of great breakthrus like STI, copper. Today they trail INTEL across the board and have resorted to constortiums to pay the bills in East Fishkill so they can pretend to be in a busines that IBM no longer leads or needs. When the world went to CMOS and IBM choose to not to do x86 IBM lost the core competence and need to be a silicon leader. Today IBM is no better at silicon then TSMC. They put a little more into performance because of PowerPC but servers sales/profts depend less on silicon then everbefore.

IBM only needs to look to the west and HP to see how it should get done. HP used to do silicon but disolved all of that years ago. And this past quarter HP leaped IBM. IBM and their white shirted CEO Sam should get out of the old blue and get with it. Silicon isn’t what is going to save or grow IBM.

Lets look more closely at some recent IBM silicon innovations or annoucments. More like lets look at some of their recent failures; SILK, bi-axial strain, HighK and now this. They are stretching to try to make the press after INTEL beat them to HighK. Lets be clear, IBM annouched HighK in a hasty response to INTEL. INTEL had demonststrated HighK in 2006 on fully functional test chips. They were very secretive then about telling the world. THen a year later they annouced it as they had committed factories and their whole future to it. IBM is annoucing nothing but a experimental result that might appear in 2009. ITs all BS that you guys are debating.

Some notable things. They talk about implemented yet it won’t appear in chips till 2009. That means it’s a 32nm technology and 32nm is still in its infancy. I’d be shocked of all the elements of 32nm are already defined and to say its for sure is another SILK like situation. Promise something only to discover it don’t work and you can’t back out and you stick it on your production only to screw your customers. You can’t figure out what will be on 32nm yet as you need to run test chips and debug and throw out things as well as invet new things. I’d believe it if it was going into 45nm next year or 65nm this year. Sorry anything revoluationary 2 years before production is suspect. Its all press noise. I'm sure even in 2006 when INTLE had their first working chip they weren't sure it was going to work.

Its also BS that they don’t use masks and chemicals.
Another BS line to impress the cluess readeers and press. They still need to pattern the metal lines and interconnects. Those don’t get hooked up by “nature.” How the hell do you form the interconnnects. Interconnects are conscious patterns drawn in a very non random and un-nature pattern. Sorry Nature doesn't pattern the interconnects. ANyone who buys that BS is a idiot!

Air/vacum gap are the holy grail for interconnects as they reduce capacitance to the theoritical limit. Kind of like HighK metal gates for the FE. Since IBM couldn’t beat INTEL there they conjured a press release for the backend. But like their Copper annoucment of a decade ago it won’t amount to much competitive product advantage for IBM nor its partner AMD.

Like silk this will type of dielectric will fall apart in the package and dice processing of the chips. In the end they will get some of this working but it won't look at all like this in 2009 I'm certain.

For another good opinion on this one go here: http://www.fabtech.org/content/view/2804/




RE: Busy IBM, more like BS from IBM.
By Crazyeyeskillah on 5/4/2007 10:55:43 PM , Rating: 2
IBM has been doing 45nm for well over 2 years


By ChipDude on 5/5/2007 12:30:04 AM , Rating: 1
There is 45nm and there is 45nm. I don't count papers about single transistors. IBM has been behind INTEL since 90nm in every important benchmark; performance, volume, functional SRAM or product


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