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Giuseppe Amato gives another overview on the high points of AMD's next-generation CPU architecture

This article was first published in German on

Yesterday, AMD held a press presentation in Munich, Germany to update journalists about its upcoming K10 processor. AMD's Giuseppe Amato, Technical Director Sales and Marketing EMEA, had a few minutes to talk about the architecture at length. This architecture, previously dubbed K8L by Henri Richard -- now publically called K10 -- is scheduled to be AMD's first monolithic quad-core design.

The integrated memory controller (IMC) will get a few new features in the K10 core. When utilizing multiple memory modules, along with proper BIOS implementation and mainboard routing, the IMC can access memory in 64-bit channels (72-bit if you use ECC). This way it is possible to read and write data simultaneously, or improve efficiency for irregular access patterns which increasingly occur in a quad-core environment. This feature is available on AM2+ and F+ boards; on "old“ socket AM2 and F boards the usual 128-bit dual-channel mode is available.

Due to split power planes, the IMC can be clocked down independently of the CPU cores, along with reduced voltage. This also enables CPU overclocking without touching the memory frequency, something that may appeal to enthusiasts. These features are again dependent on Socket AM2+ and F+ platforms.

Amato explained how the quad-core design benefits from the internal crossbar switch the backbone of communication inside the K10 CPU. With Intel's current quad-core design there are cases where data needs to travel over the FSB -- in AMDs case all inter-CPU communication takes place on-die.

The crossbar switch of the K10 core is already prepared for up to 8 cores, Amato boasted. Amato wouldn't give even a vague timeframe for market availability of such a CPU, though he indicated the company is prepared for whatever the market demands. Amato made clear that octo-core is far away in the future – Shanghai will not get 8 cores.

K10 will introduce a shared L3 cache while the individual cores have dedicated L1 and L2 caches. As long as requested data lies in L1, it can be directly loaded. This also works if the data lies in the L1 cache of another core, in which case the communication works via the crossbar switch. In case requested data resides in the L2 cache, it will be loaded to L1 and then invalidated in L2 as AMD has an exclusive cache design. The L3 Cache, however, is not exclusive, but allows for a shared bit to be set. If a core loads data marked as shared, it will reside in the L3 cache and can be fetched by other cores as well.

Amato also mentioned an array of power saving measures which, in sum, allow AMD to deliver a quad-core CPU in the same thermal envelope as today’s dual-core CPUs.

K10 adds the capability of independently clocking all the CPU cores. In current K8 processors (and Intel's Core 2 generation), all cores are clocked at the same level all the time -- the P-state can only be changed synchronously. In case of a compute-intensive single-threaded process, all cores must run on the highest level P-state. On K10-based CPUs, the idle cores could be switched to the lowest P-state, while others are in different states, depending on load.

This feature could possibly be abused by overclockers to overclock a single core above the specified levels. Amato clarified that AMD doesn't endorse overclocking, but acknowledges there are people interested in that. In a warranty case, AMD could detect PLL programmings out of spec which would deny the warranty. The new cores, however, have new thermal sensors, to improve overheating protection.

Amato closed the session by mentioning Shanghai as a successor to Barcelona in the server space for 2008. Shanghai will be an improved quad-core architecture, which is supposed to be socket-compatible with current Socket F platforms. Roadmaps available to DailyTech revealed Shanghai is a 45nm quad-core CPU featuring 6MB of L3 Cache.

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RE: A little pleased
By Griswold on 4/16/2007 8:19:29 AM , Rating: 3
My main concern is the lack of information on the more fundamental aspects of a CPU: AMD does not seem overly-concerned with expressing how it's going to raise its power:performance to a more-competitive level with Intel.

What do you expect? They can provide as many details and internal performance numbers as they like, there will always be doubt until the benchmarks are verified - in fact, they have been giving out details and numbers over the last months, and its been received exactly as I said above, for the most part.

RE: A little pleased
By Marcus Pollice on 4/16/2007 8:46:20 AM , Rating: 2
The only performance numbers that were given at the event were the same 40% advantage over Clovertown in FP-heavy code (SPECfp).

RE: A little pleased
By jhtrico1850 on 4/16/2007 3:40:20 PM , Rating: 2
And that's on the older SPECfp_rate2000 too.

RE: A little pleased
By Dactyl on 4/16/2007 4:49:38 PM , Rating: 2
The 40% SPECfp advantage vs. Clovertown doesn't tell us much.

That benchmark scales poorly for Intel when you go from Core 2 Duo to Core 2 Quad .

Is that because SPECfp is FSB-limited on a Clovertown?

But how many of the applications you and me care about (games, etc.) are FSB-limited?

Why is AMD only showing a single, cherry-picked benchmark?

Like I've said before, I want to be wrong about this. I want Barcelona to crush Penryn. But the indications so far are not promising.

RE: A little pleased
By Lakku on 4/16/2007 6:59:16 PM , Rating: 2
Well, it has to deal with the Core 2/Kentsfield CPUs first. I say this because Intel has been stating that they plan on having Penryn up into the mid 3GHz range, or at the least, clocked well above what Kentsfield is now. I am guessing Barcelona will probably be faster per clock, but Intel may just ramp up speeds to counter that advantage. With that said, I am sure Barcelona will contiunue to keep AMD competative or in the lead in the server realm, but a 'native' quad-core may not really matter when it comes to what most of care about here, and that is games/home computing (ripping, movie making, etc.).

RE: A little pleased
By Dactyl on 4/16/07, Rating: -1
RE: A little pleased
By IamKindaHungry on 4/16/2007 8:48:05 PM , Rating: 4
What would you rather have: an efficient crossbar linking your native quad core CPU, or an additional 5 FPS in S.T.A.L.K.E.R.?

Actually, I choose option #3 which is a another patch for all the bugs in S.T.A.L.K.E.R.

"If you look at the last five years, if you look at what major innovations have occurred in computing technology, every single one of them came from AMD. Not a single innovation came from Intel." -- AMD CEO Hector Ruiz in 2007

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