Intel Readies Merom-L Core
April 7, 2007 9:16 PM
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In a bid to make manufacturing of Celeron M 500 CPUs economically more efficient, Intel will introduce a shrunk-down core in the near future.
Last January Intel introduced the Celeron M 520, a low-cost entry-level mobile CPU based on Core microarchitecture. At $134 the CPU was relatively low-cost from a consumer point of view -- with scheduled price drop to $107 on April 22nd. Under the hood the CPU featured a "fully fledged" Merom core with the current B2 stepping. It's safe to assume that these feature at least 2 cores and 2MB L2 Cache -- given the processors have different manufacturing lines for 4MB and 2MB models.
In the recent
Intel notified its customers about a stepping change for Celeron M 520. Although a Celeron M 530 was introduced on March 25th at $134, in the PCN this model is not mentioned at all. Intel informs that said model will transition from a Merom B2 stepping core to a new
Merom-L core with A stepping
, which will be available starting the 1st of June.
The only change for customers is a different CPUID which requires a BIOS update along with a microcode update in oder to support the CPU correctly. Besides Intel notes that "Merom-L A stepping material has minor die size decrease due to manufacturing optimizations to
increase product availability".
As the PCN only mentions a minor die size decrease it remains open whether Intel only reduced the L2 cache down to 1MB or also managed to cut off one of the two CPU cores. My bet is on L2 Cache only, as it explicitly mentions "minor" and the CPU cores in Core-based CPUs are linked kinda tightly so it would have required some sort of redesign of the chip.
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4/8/2007 3:05:28 AM
The 667 celeron was great too as it would easily ratchet up to a quick 1GHz when those CPUs were pulling $600 a pop and only for about a $100 chip!
As for the celeron's "bad" performance, the celeron was actually a very good performer with the exception of two versions: The Pentium II celeron (pre-A versions ala 300 vs 300A) that had zero L2 cache (just stupid with the P6 core) and the initial P4 celerons (which had their cache associativity cut way down).
4/8/2007 7:17:29 AM
Actually doing some tests I found out that a Katmai Pentium 3 500-512k of cache-133mhz FSB performed about the same as a 700Mhz Celeron.
The celerons not only were restricted to a 66Mhz bus in those days, Where the Pentium 3 used 100/133mhz buses, (Thats like 50%-100% bandwidth difference)
But they used 128k of on-die cache, Which was half of the coppermine and 1/4th the amount on the katmai, Now not only did it have its cache severely cut done, but the celeron only had four-way set associative on die L2 , While the Pentium 3 had 8-way, And cache latency's were much higher.
In 3D mark 2000 the Pentium 3 at the same clock speed as a celeron with a 100mhz FSB performed about 1000 3D marks slower. Which was really noticeable for back then. And back then, I prefer the AMD K6-2 Socket 7, then moved onto the K6-3 then the Pentium 3.
Back when the Celeron was against the Pentium 2, The cache was actually in a better configuration, As it was full speed on-die, Whilst the Pentium 2 was 256/512 off die cache.
"There's no chance that the iPhone is going to get any significant market share. No chance." -- Microsoft CEO Steve Ballmer
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