backtop


Print 10 comment(s) - last by Anonymous Frea.. on Apr 9 at 2:26 PM

In a bid to make manufacturing of Celeron M 500 CPUs economically more efficient, Intel will introduce a shrunk-down core in the near future.

Last January Intel introduced the Celeron M 520, a low-cost entry-level mobile CPU based on Core microarchitecture. At $134 the CPU was relatively low-cost from a consumer point of view -- with scheduled price drop to $107 on April 22nd. Under the hood the CPU featured a "fully fledged" Merom core with the current B2 stepping. It's safe to assume that these feature at least 2 cores and 2MB L2 Cache -- given the processors have different manufacturing lines for 4MB and 2MB models.

In the recent PCN 107423-00 Intel notified its customers about a stepping change for Celeron M 520. Although a Celeron M 530 was introduced on March 25th at $134, in the PCN this model is not mentioned at all. Intel informs that said model will transition from a Merom B2 stepping core to a new Merom-L core with A stepping, which will be available starting the 1st of June.

The only change for customers is a different CPUID which requires a BIOS update along with a microcode update in oder to support the CPU correctly. Besides Intel notes that "Merom-L A stepping material has minor die size decrease due to manufacturing optimizations to
increase product availability".

As the PCN only mentions a minor die size decrease it remains open whether Intel only reduced the L2 cache down to 1MB or also managed to cut off one of the two CPU cores. My bet is on L2 Cache only, as it explicitly mentions "minor" and the CPU cores in Core-based CPUs are linked kinda tightly so it would have required some sort of redesign of the chip.


Comments     Threshold


This article is over a month old, voting and posting comments is disabled

RE: Celery!
By tehfire on 4/8/2007 1:40:16 AM , Rating: 2
fdqwI don't think it was the restricted FSB so much as it was the lacking L2. An inclusive cache just does not take an L2 cache decrease very well. Of course, then decreasing the FSB bandwidth just when the processor needs it most doesn't help it either...

Typing with 4 fingers, football accident. Really lazy in typing and not explaining. Why do we geeks have to be so clumsy? :-P


RE: Celery!
By Ringold on 4/8/2007 4:16:08 PM , Rating: 2
Geeks play football..?

Just teasing :)


RE: Celery!
By Anonymous Freak on 4/9/2007 2:26:36 PM , Rating: 2
It's almost certainly the cache. I had a 1.4 GHz Celeron-M notebook (1 MB L2 cache,) that runs circles around a 2.8 GHz Celeron-D desktop (256 KB L2 cache,) with otherwise identical specs. (Both 915 chipset, both 512 MB dual-channel DDR2-533 memory.) And the desktop has an 533 MHz bus compared to the mobile's 400 MHz bus. I know the Pentium-M core is more efficient than the NetBurst core, but to the tune of more than double? The larger cache HAS to be the difference. I later upgraded the notebook to a Pentium-M 2.26 GHz and there really was very little noticable performance improvement, it took benchmarks to see the difference. When I upgraded the desktop to a Pentium 4 3.2 GHz, on the other hand, it was night-and-day.


"This week I got an iPhone. This weekend I got four chargers so I can keep it charged everywhere I go and a land line so I can actually make phone calls." -- Facebook CEO Mark Zuckerberg

Related Articles













botimage
Copyright 2014 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki