Intel Life After "Penryn"
March 28, 2007 10:33 AM
comment(s) - last by
The bell tolls for "Nehalem" when Intel's clock strikes next in 2008
More details of Intel's next-generation architecture unveiled
Intel's "tick tock" development cycle continues to chime with the
processor architecture scheduled for production next year. Intel Senior Vice President Pat Gelsinger detailed the advanced features on the next-generation to
In the second half of this year, Intel will release its first
. While nearly identical architecturally to the Core 2 Duo processors released last year,
's 45nm node allows Intel to put more L2 cache onboard; the company already announced
-based processors will utilize up to 12MB of L2 cache on quad-core designs.
Intel's 45nm node utilizes metal transistor gates and high-k dielectrics. The departure from silicon-based transistors
translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage. According to Intel guidance, this means existing processors could run 20% faster just by switching to metal gate and high-k transistors. Gelsinger claims mature
processors will operate in excess of 3 GHz per core, with 1600 MHz front-side busses on server platforms.
After the 45nm shrink has matured, Intel will then incorporate architectural changes into its processor family, currently dubbed
is still a 4-issue architecture similar to Core, but new advances in management and scalability give
its new micro architecture designation.
Earlier this year Intel roadmaps stated Hyper-Threading would appear on some
processors. Shortly after,
Intel retracted the roadmap
, stating that simultaneous multi-threading will not reappear until 2008. This was made evident today when Intel unveiled its next-generation threading plans for
-family processors have eight cores. Coupled with 2-way threading, these processors appear as 16 logical CPUs. This threading is dynamic: Threads can be powered on and off depending on the application needs.
Dynamic threading isn't the only on-the-fly operation for
. Almost everything about
can be dynamically managed: Power, threads, bus, cache and cores. This management is primarily a power-saving feature, but also allows for saleable designs as well.
The bulk of these changes are possible due to
's on-board memory controller. AMD realized the advantages of integrated memory controllers (IMCs) with the introduction of its Opteron series processors four years ago. Intel has long toyed with with IMCs on some processors, and will even
system-on-a-chip later this year
with an integrated memory controller.
Intel's dynamic bus, the Common System Interface (CSI), is clearly a focal point for the
architecture. With many respects, CSI is very similar to HyperTransport: Variable, serial interconnects for processor-to-processor communication. CSI will not only make its debut on
, but design engineers have also confirmed to
that CSI will have
a large presence on next-generation Itanium platforms as well
Intel leaves a single teaser in its
design guidance: "High performance integrated graphics engine for client." Speaking on background, Intel insiders stated "The majority of the Intel Northbridge is already on the
die, so adding the final logic to include graphics is essentially [trivial] with the correct bus support." Intel's
renewed interest in graphics processing
came just weeks after AMD made similiar announcements, which
AMD has codenamed
In addition, Intel will also expand the SSE4 instruction set. Other architectural tweaks include shared multi-level cache. AMD's upcoming
processors share L3 cache between cores; Intel's last
processors shared L3 cache, but no current Core processor utilizes such functionality.
Gelsinger emphasizes that
is on track for production in 2008.
Intel's "tick tock" strategy doesn't end at the 45nm node. In 2009 Intel will optically shrink
process from 45nm to 32nm. In a sense, it's the same move Intel is currently undertaking with the transition from
's 32nm shrink is dubbed
. The 32nm architecture that will succeed
This article is over a month old, voting and posting comments is disabled
RE: AMD's future is doomed
3/31/2007 3:43:59 PM
Barcelona will be able to execute 128bit SSE instructions two times as fast as the current Core 2 architecture since it can load, execute, and retire 2 128 bit SSE instructions vs. Core 2's 1 (which was still two times faster than K8 or P4 could do it).
Barcelona also sports most of the improvements that Core 2 got over Yonah.
In addition to all of that, Barcelona has L3 cache and an exclusive L2 (lower latency than a shared L2 that C2D has).
In addition to ALL of that, K8 and its derivatives have always had a superior FP unit.
Add all that up ..... you still think that Barcelona isn't going to cause Intel some grief?
Here is a clue ..... Intel is planning to SLASH its desktop prices by 300% in Q3 2007. Why do you suppose that is?
RE: AMD's future is doomed
4/1/2007 12:41:44 PM
Attributing Intel's price cuts, automatically, to purported superiority of Barcelona is foolish.
"Game reviewers fought each other to write the most glowing coverage possible for the powerhouse Sony, MS systems. Reviewers flipped coins to see who would review the Nintendo Wii. The losers got stuck with the job." -- Andy Marken
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