Intel Life After "Penryn"
March 28, 2007 10:33 AM
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The bell tolls for "Nehalem" when Intel's clock strikes next in 2008
More details of Intel's next-generation architecture unveiled
Intel's "tick tock" development cycle continues to chime with the
processor architecture scheduled for production next year. Intel Senior Vice President Pat Gelsinger detailed the advanced features on the next-generation to
In the second half of this year, Intel will release its first
. While nearly identical architecturally to the Core 2 Duo processors released last year,
's 45nm node allows Intel to put more L2 cache onboard; the company already announced
-based processors will utilize up to 12MB of L2 cache on quad-core designs.
Intel's 45nm node utilizes metal transistor gates and high-k dielectrics. The departure from silicon-based transistors
translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage. According to Intel guidance, this means existing processors could run 20% faster just by switching to metal gate and high-k transistors. Gelsinger claims mature
processors will operate in excess of 3 GHz per core, with 1600 MHz front-side busses on server platforms.
After the 45nm shrink has matured, Intel will then incorporate architectural changes into its processor family, currently dubbed
is still a 4-issue architecture similar to Core, but new advances in management and scalability give
its new micro architecture designation.
Earlier this year Intel roadmaps stated Hyper-Threading would appear on some
processors. Shortly after,
Intel retracted the roadmap
, stating that simultaneous multi-threading will not reappear until 2008. This was made evident today when Intel unveiled its next-generation threading plans for
-family processors have eight cores. Coupled with 2-way threading, these processors appear as 16 logical CPUs. This threading is dynamic: Threads can be powered on and off depending on the application needs.
Dynamic threading isn't the only on-the-fly operation for
. Almost everything about
can be dynamically managed: Power, threads, bus, cache and cores. This management is primarily a power-saving feature, but also allows for saleable designs as well.
The bulk of these changes are possible due to
's on-board memory controller. AMD realized the advantages of integrated memory controllers (IMCs) with the introduction of its Opteron series processors four years ago. Intel has long toyed with with IMCs on some processors, and will even
system-on-a-chip later this year
with an integrated memory controller.
Intel's dynamic bus, the Common System Interface (CSI), is clearly a focal point for the
architecture. With many respects, CSI is very similar to HyperTransport: Variable, serial interconnects for processor-to-processor communication. CSI will not only make its debut on
, but design engineers have also confirmed to
that CSI will have
a large presence on next-generation Itanium platforms as well
Intel leaves a single teaser in its
design guidance: "High performance integrated graphics engine for client." Speaking on background, Intel insiders stated "The majority of the Intel Northbridge is already on the
die, so adding the final logic to include graphics is essentially [trivial] with the correct bus support." Intel's
renewed interest in graphics processing
came just weeks after AMD made similiar announcements, which
AMD has codenamed
In addition, Intel will also expand the SSE4 instruction set. Other architectural tweaks include shared multi-level cache. AMD's upcoming
processors share L3 cache between cores; Intel's last
processors shared L3 cache, but no current Core processor utilizes such functionality.
Gelsinger emphasizes that
is on track for production in 2008.
Intel's "tick tock" strategy doesn't end at the 45nm node. In 2009 Intel will optically shrink
process from 45nm to 32nm. In a sense, it's the same move Intel is currently undertaking with the transition from
's 32nm shrink is dubbed
. The 32nm architecture that will succeed
This article is over a month old, voting and posting comments is disabled
RE: AMD is Effed
3/30/2007 10:38:49 AM
AMD has been lacking in the last couple of months as the K8 architecture has been brought to an early death by core 2, that's probably the only fact that anyone sane could agree on. We never know what will happen with Intel or AMD but it's already been said that Intel took heavy hits in the profit department in Q3 or 4 (can't remember) of last year and AMD will have to step up production when Barcelona comes out. AMD is also stuck facing a cheap, well received chip that many people have in their systems, and not as many people will jump on upgrading to Barcelona unless it's VERY cheap and MUCH better than Core 2. Intel finished Core 2 and fired 10000 employees, no doubt many of those that were fired did serious development work on the Core 2 project who are now possibly working for AMD. When it comes time to redevelop an architecture, Intel probably won't be able to make as large a leap as Core 2.
RE: AMD is Effed
3/31/2007 2:52:24 AM
Dude.. STFU. you don't know your facts so shut up. Intel fired most of the non-essential people-- like 1,000 managers and people from marketing. They cut projects that were just sucking the life and limb out if intel. I KNOW there were software developers who did jack squat.
encriptkeeper, You do not know what you are talking about.
AMD is in trouble. Barcelona will get its L2 cache(essentially its buttocks) handed to itself when penryn shows up. MCM with onboard memory controller and northbridge on die means dark times for AMD.
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