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The bell tolls for "Nehalem" when Intel's clock strikes next in 2008
More details of Intel's next-generation architecture unveiled

Intel's "tick tock" development cycle continues to chime with the Nehalem processor architecture scheduled for production next year. Intel Senior Vice President Pat Gelsinger detailed the advanced features on the next-generation to DailyTech earlier today.

In the second half of this year, Intel will release its first 45nm Penryn-based processors.  While nearly identical architecturally to the Core 2 Duo processors released last year, Penryn's 45nm node allows Intel to put more L2 cache onboard; the company already announced Penryn-based processors will utilize up to 12MB of L2 cache on quad-core designs.

Intel's 45nm node utilizes metal transistor gates and high-k dielectrics.  The departure from silicon-based transistors translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage.  According to Intel guidance, this means existing processors could run 20% faster just by switching to metal gate and high-k transistors.  Gelsinger claims mature Penryn processors will operate in excess of 3 GHz per core, with 1600 MHz front-side busses on server platforms.

After the 45nm shrink has matured, Intel will then incorporate architectural changes into its processor family, currently dubbed NehalemNehalem is still a 4-issue architecture similar to Core, but new advances in management and scalability give Nehalem its new micro architecture designation.

Earlier this year Intel roadmaps stated Hyper-Threading would appear on some Penryn processors.  Shortly after, Intel retracted the roadmap, stating that simultaneous multi-threading will not reappear until 2008.  This was made evident today when Intel unveiled its next-generation threading plans for Nehalem.

High-end server Nehalem-family processors have eight cores. Coupled with 2-way threading, these processors appear as 16 logical CPUs.  This threading is dynamic: Threads can be powered on and off depending on the application needs.

Dynamic threading isn't the only on-the-fly operation for Nehalem.  Almost everything about Nehalem can be dynamically managed: Power, threads, bus, cache and cores.  This management is primarily a power-saving feature, but also allows for saleable designs as well.

The bulk of these changes are possible due to Nehalem's on-board memory controller.  AMD realized the advantages of integrated memory controllers (IMCs) with the introduction of its Opteron series processors four years ago.  Intel has long toyed with with IMCs on some processors, and will even deliver the Tolapai system-on-a-chip later this year with an integrated memory controller.

Intel's dynamic bus, the Common System Interface (CSI), is clearly a focal point for the Nehalem architecture.  With many respects, CSI is very similar to HyperTransport: Variable, serial interconnects for processor-to-processor communication.  CSI will not only make its debut on Nehalem, but design engineers have also confirmed to DailyTech that CSI will have a large presence on next-generation Itanium platforms as well.

Intel leaves a single teaser in its Nehalem design guidance: "High performance integrated graphics engine for client."  Speaking on background, Intel insiders stated "The majority of the Intel Northbridge is already on the Nehalem die, so adding the final logic to include graphics is essentially [trivial] with the correct bus support."  Intel's renewed interest in graphics processing came just weeks after AMD made similiar announcements, which AMD has codenamed Fusion.

In addition, Intel will also expand the SSE4 instruction set.  Other architectural tweaks include shared multi-level cache.  AMD's upcoming Barcelona processors share L3 cache between cores; Intel's last NetBurst processors shared L3 cache, but no current Core processor utilizes such functionality.

Gelsinger emphasizes that Nehalem is on track for production in 2008.

Intel's "tick tock" strategy doesn't end at the 45nm node.  In 2009 Intel will optically shrink Nehalem process from 45nm to 32nm.  In a sense, it's the same move Intel is currently undertaking with the transition from Conroe to PenrynNehalem's 32nm shrink is dubbed Westmere.  The 32nm architecture that will succeed Westmere is dubbed Gesher.


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RE: AMD is Effed
By defter on 3/29/2007 5:42:49 AM , Rating: 5
Actually, anybody that has followed AMD's statements recently have a pretty good idea on those issues:

- based on AMD's Barcelona peformance claims, it's very, very likely that Barcelona will be slower in the desktop (1S) compared to Penryn based quad cores that will be able to reach 3.6GHz in Q1 2008.
- AMD has stated that they plan to have 45nm chips available in mid-2008. Thus they will be at least 6 months behind Intel. However, considering AMD's delays with previous process transitions, it's likely that 45nm process will be delayed to late 2008.
- AMD has always disclosed details about future architecture improvements well in advance. Athlon details were disclosed in 1998, almost a year before launch. K8 details were disclosed in Autumn 2001, 1.5 years before Opteron launch. Last summer AMD disclosed Barcelona details, more than a year before availability. So far there has been zero information about AMD's architecture improvements scheduled for the next year, there haven't been any rumours let alone official information. Thus, it's safe to say that there won't be anything drastically new (45nm shrink doesn't count) from AMD in 2008.


RE: AMD is Effed
By Viditor on 3/31/2007 11:37:32 AM , Rating: 2
quote:
based on AMD's Barcelona peformance claims, it's very, very likely that Barcelona will be slower in the desktop (1S) compared to Penryn based quad cores that will be able to reach 3.6GHz in Q1 2008


This is incorrect...
1. Even a K8 core on a quad core configuration is faster than C2D. That's already been benched (in a roundabout manner). The benchmarks show that a 2P dual core Opteron is about the same as a Clovertown (QC), and we know from when Opteron went dual core that it gains ~5% when the cores are placed on the same die. A 4P Opteron is ~16% faster than a 2P Clovertown...

2. Barcelona is to be 42% faster in FP and "double digits" faster in integer than Clovertown, but the K10s that follow Barcelona in Q3 (still before Penryn's release) will be even faster as they will be using HT 3.0 (unlike Barcelona).

3. We still have no idea how high the K10s will clock yet...

quote:
However, considering AMD's delays with previous process transitions, it's likely that 45nm process will be delayed to late 2008

This is a ridiculous thing to say...it's like saying Nehalem will be delayed by 3 more years because Itanium was.
quote:
AMD has always disclosed details about future architecture improvements well in advance

Firstly, most of those examples were about Jerry Sanders and AMD, not Hector.
Secondly, even if that bizarre logic holds true, we shouldn't see any architecure announcements until July for the 45nm...that will be 1 year before release.


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