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The bell tolls for "Nehalem" when Intel's clock strikes next in 2008
More details of Intel's next-generation architecture unveiled

Intel's "tick tock" development cycle continues to chime with the Nehalem processor architecture scheduled for production next year. Intel Senior Vice President Pat Gelsinger detailed the advanced features on the next-generation to DailyTech earlier today.

In the second half of this year, Intel will release its first 45nm Penryn-based processors.  While nearly identical architecturally to the Core 2 Duo processors released last year, Penryn's 45nm node allows Intel to put more L2 cache onboard; the company already announced Penryn-based processors will utilize up to 12MB of L2 cache on quad-core designs.

Intel's 45nm node utilizes metal transistor gates and high-k dielectrics.  The departure from silicon-based transistors translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage.  According to Intel guidance, this means existing processors could run 20% faster just by switching to metal gate and high-k transistors.  Gelsinger claims mature Penryn processors will operate in excess of 3 GHz per core, with 1600 MHz front-side busses on server platforms.

After the 45nm shrink has matured, Intel will then incorporate architectural changes into its processor family, currently dubbed NehalemNehalem is still a 4-issue architecture similar to Core, but new advances in management and scalability give Nehalem its new micro architecture designation.

Earlier this year Intel roadmaps stated Hyper-Threading would appear on some Penryn processors.  Shortly after, Intel retracted the roadmap, stating that simultaneous multi-threading will not reappear until 2008.  This was made evident today when Intel unveiled its next-generation threading plans for Nehalem.

High-end server Nehalem-family processors have eight cores. Coupled with 2-way threading, these processors appear as 16 logical CPUs.  This threading is dynamic: Threads can be powered on and off depending on the application needs.

Dynamic threading isn't the only on-the-fly operation for Nehalem.  Almost everything about Nehalem can be dynamically managed: Power, threads, bus, cache and cores.  This management is primarily a power-saving feature, but also allows for saleable designs as well.

The bulk of these changes are possible due to Nehalem's on-board memory controller.  AMD realized the advantages of integrated memory controllers (IMCs) with the introduction of its Opteron series processors four years ago.  Intel has long toyed with with IMCs on some processors, and will even deliver the Tolapai system-on-a-chip later this year with an integrated memory controller.

Intel's dynamic bus, the Common System Interface (CSI), is clearly a focal point for the Nehalem architecture.  With many respects, CSI is very similar to HyperTransport: Variable, serial interconnects for processor-to-processor communication.  CSI will not only make its debut on Nehalem, but design engineers have also confirmed to DailyTech that CSI will have a large presence on next-generation Itanium platforms as well.

Intel leaves a single teaser in its Nehalem design guidance: "High performance integrated graphics engine for client."  Speaking on background, Intel insiders stated "The majority of the Intel Northbridge is already on the Nehalem die, so adding the final logic to include graphics is essentially [trivial] with the correct bus support."  Intel's renewed interest in graphics processing came just weeks after AMD made similiar announcements, which AMD has codenamed Fusion.

In addition, Intel will also expand the SSE4 instruction set.  Other architectural tweaks include shared multi-level cache.  AMD's upcoming Barcelona processors share L3 cache between cores; Intel's last NetBurst processors shared L3 cache, but no current Core processor utilizes such functionality.

Gelsinger emphasizes that Nehalem is on track for production in 2008.

Intel's "tick tock" strategy doesn't end at the 45nm node.  In 2009 Intel will optically shrink Nehalem process from 45nm to 32nm.  In a sense, it's the same move Intel is currently undertaking with the transition from Conroe to PenrynNehalem's 32nm shrink is dubbed Westmere.  The 32nm architecture that will succeed Westmere is dubbed Gesher.


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RE: AMD's future is doomed
By murphyslabrat on 3/28/2007 7:11:41 PM , Rating: 2
The problem here is that Intel is a shoolyard bully that is being harried by the pipsqueek AMD. For the past several years Intel had a seriously debilitating desease called NetBurst. Now after that has been cured, Intel has been bringing it's great financial superiority to a project that is worthwhile; the result? AMD is, again, an underdog with less than a little more than a quarter of the money to play with than Intel.
My take of the situation is that AMD will be the next VIA, albeit a VIA with CPU's, GPU's, and chipsets that don't suck; but an underdog nonetheless. For those of us who love cheap PC's(that don't overheat while playing Solitaire) AMD will be our solution.
Whatever the case, AMD IS and HAS been the underdog, and that's what we love them for. Fortunately, they have given us much better performance than Intel's offerings till now, but that's the way the conoe(is that the proper spelling? if it is, the similiarity to 'conroe' is funny) floats. For you people who are foretelling Doom and Gloom for AMD, that is the nature of this industry.
And, to conclude, worst case scenario: AMD(or DAAMIT) gets bought by a company with a vastly greater financial basis. This is what happened with Voodoo(for those of you who remember those days) and ATI, and we'll see better products from a rebranded company.


RE: AMD's future is doomed
By cheetah2k on 3/28/07, Rating: 0
RE: AMD's future is doomed
By cheetah2k on 3/29/2007 9:55:56 PM , Rating: 2
Man, the Intel fanboys are out in force today LOL


"We don't know how to make a $500 computer that's not a piece of junk." -- Apple CEO Steve Jobs

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