AMD Claims 5-hour Battery Life for Turion Notebooks in 2007
March 17, 2007 6:32 PM
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AMD is poised to square its next-generation tech against Intel's "Santa Rosa"
AMD is set to launch its upcoming K10 architecture with the
quad-core server processor
. However, since the
ATI acquisition last year
, AMD has also focused extensively on its mobile roadmap.
This May, Intel's Centrino platform will enter its fourth revision with
. Late last year AMD launched the
platform -- 90nm dual-core Turion processors, DDR2-667 and 802.11g wireless.
will undergo a refresh at about the same time as the Intel
The spearhead of this new initiative is the
-family of mobile CPUs. The first of these new Turion CPUs,
, is a 65nm SOI DDR2-800 processor that utilizes Socket S1. Essentially, this processor is
for the notebook
, and does not incorporate any of the
new features of the K10/
, a low cost 65nm SOI revision dubbed
will replace the 90nm Mobile Sempron cores.
Although AMD states its upcoming mobile platform is a collaboration between AMD and ATI, ATI's contribution has been in the works for almost two years -- well before the AMD merger. Earlier this year,
AMD leaked details of its
mobile reference design
detailing the exact component breakout for next generation Turion notebooks.
At the heart of the 2007
refresh is the RS690T chipset -- a low-power version of the
RS690 chipset found on the desktop
. Graphics are provided by a Radeon X700 derivative core; system IO functionality revolves around the SB700 southbridge.
's design kit also outlines the use of hybrid hard drives and 802.11n-draft wireless.
AMD guidance specifically details the transition from its 90nm to 65nm, in addition to the advances of the RS690 chipset, will boost Turion notebook battery life from 4 hours to in excess of 5 hours.
In 2008 AMD will reveal its
-family of CPUs. AMD guidance claims these CPUs are built from the ground up to utilize mobile technology, though the processors have been on AMD's roadmap for more than a year as
derivatives. The first of these,
, will replace
in the first half of 2008. The low-cost
on the Sempron platform.
All of the
processors will utilize HyperTransport 3 and 65nm SOI. A cornerstone of the K10 (previously dubbed K8L) architecture is split power planes -- the CPU can dynamically adjust p-states on individual cores or the integrated northbridge. Currently no commercial processors can do this sort of power management, which has potential to save big on power consumption.
This article is over a month old, voting and posting comments is disabled
RE: "the CPU can dynamically adjust p-states on individual cores "
3/18/2007 5:25:31 PM
The Core architecture can do this with c-states, not p-states.
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