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"Torrenza" systems will accept both multi-core, accelerators, or "Fusion" processors
AMD sheds more light on accelerated processing projects

This week at CeBIT 2007, AMD revealed more details about its "accelerated computing" platform, codenamed Torrenza. AMD's goal behind Torrenza is to create a platform where application-specific processors can interact cost effectively and offer better performance than a general purpose CPU, while remaining compatible with off the shelf platforms.

AMD guidance revealed this week that future processors will also have integrated "accelerators" embedded into them. A Torrenza system will have at least two sockets, and both will accept accelerators and accelerated CPUs.

One accelerated-processor project on AMD plate, slated for 2008 under the codename Fusion, and combines a dedicated GPU or GPU accelerator onto the same package or even the same silicon die as the main CPU. AMD has already set the ground-work for Fusion processing with its Stream Computing initiative -- utilizing ATI-based graphics adaptors for heavy number crunching. 

Other Torrenza ready projects are also coming to light.  Clearspeed announced its CSX600 math-coprocessor plug-in last year, with the stated intention of creating a socket plugin version for Torrenza.  Los Alamos National Labs is currently building the world's fastest supercomputer, Roadrunner, with Opteron and Cell processors on the Torrenza platform.

Torrenza is not just locked within the compounds of the CPU sockets. According to AMD, Torrenza systems will accept accelerators in a PCI-Express interface too, allow for multiple application specific accelerators to access system memory and processor functions directly.  Mercury systems announced a PCIe plug-in accelerator late last year.

While Torrenza is well on its way to seeing daylight, Intel is also working on its own open architecture platform. Notorious for keeping its CPU platform a closely guarded technology, Intel indicated that it was working on a competitive technology to AMD's HyperTransport, dubbed CSI, allowing direct CPU and memory access.

Intel guidance suggests the company will announce its Torrenza competitor sometime in mid-2008.


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By coldpower27 on 3/19/2007 3:38:47 PM , Rating: 2
quote:
A chip die with 2 R600 cores and 2 Barcelona cores would be the largest cpu ever. The R600 is rumored to be well above 600 million transistors, so 2 of the is over 1.2 billion. The current dual core K8 chips are roughly 227 million transistors, so even if we say the Barcelona has the same number of trasistors as K8 (which it won't) this brings us to a total of 1.4 billion transistors. Conroe at 65nm (with 4MB of cache) is roughly 300 million transistors and 143mm^2. At 45nm you could fit roughly 600 million transistors in that same 143mm^2. This means that the chip you described would be more than double that size at around 300mm^2.


You also got to keep in mind transistor density. Even on the 45nm node something to that extreme is highly improbable. Barcelona is coming in on 283 mm2 with 463 mil transistors on the 65nm node. On the CPU side perfect optical shrinks do not happen and are at least 10% higher then the perfect shrink so your looking at around 60% the size of the 65nm version for Barcelona at 45nm node. On the 45nm node Barcelona would be about 170mm2 each, 2 of those would be 340mm2 and that only covers the CPU's. The rumored value for the R600 is 700 Million or so a bit more then the G80.

AMD's Fusion would likely be something on the magnitude of 1 R600 Core and 1 Barcelona on the 45nm node, which would still be quite the interesting product.

Remember it has to be viable and not super costly to produce.


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