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Intel's Teraflops Research Chip runs on an LGA socket at 62W
Six months after its initial debut, Intel sheds more light on the massively parallel teraflop-on-a-chip project

With no Spring Intel Developer Forum in the U.S., Intel is showing off its newest technologies this week at the annual Integrated Solid State Circuits Conference (ISSCC) in San Francisco. At the forefront of Intel’s announcements is its success in developing the world’s first 80-core processor, currently presented at ISSCC.

Intel’s chief technology officer, Justin Rattner, states "Our researchers have achieved a wonderful and key milestone in terms of being able to drive multi-core and parallel computing performance forward. It points the way to the near future when Teraflop-capable designs will be commonplace and will reshape what we can all expect from our computers and the Internet at home and in the office."

The project until now was previously dubbed Tera-scale at public Intel events.  The proper name is now the Intel Teraflops Research Chip -- alluding to the fact the processor can achieve one trillion FLoating-point Operations Per Second. Tera-scale made its first appearance during the Fall 2007 Intel Developer Forum in September 2006.  The ISSCC agenda published last month shed more details on the architecture, but this past weekend Intel pulled out most of the stops.

The Teraflops Research Chip is composed of a total of 80 independent processing cores, which Intel refers to as tiles. The tiles are organized in rectangular fashion, with 8 tiles placed across and 10 down, adding up to a total of 80.

Each individual tile in the chip features a processing engine (PE) and a 5-port router. The router passes data and instructions to other tiles, while the processing engine, as the name indicates, processes data. To save power, each processing engine can power down independently of its router, meaning that a tile can theoretically only be used to pass data when its processing engine is not needed. The processing engine can then be turned on to process additional data on-demand.  Intel's guidance claims the processor can achieve one teraflops performance on just 62W of power.

The chip itself uses an LGA package similar to Intel’s Core 2 and Pentium 4 processors. A clear difference, however, is that is uses 1248 pins in place of 775. Intel's guidance states that 343 pins are used for signaling, while the rest are used for power and ground.

The minimum clock speed the chip needs to run at in order to process one teraflop is 3.16 GHz per core at 0.95V, but Intel's guidance already alludes at frequencies in excess of 5.7 GHz.  Performance, at this time, appears linear; a 5.7 GHz Teraflops Research Chip has an output of 1.81 teraflops.

Intel has large plans for its Teraflops Research Chip. The primary purpose of the chip and project is less to make record performances, and more to serve as a vessel to test future Intel technologies. The next major technologies Intel will be implementing in the Tera-scale research project will be 3-D stacked memory and introducing more general purpose and capable cores.

A major limitation of the current 80-core chip is that it is not based on the X86 architecture. Instead, it uses a 96-bit Very Long Instruction Word (VLIW) architecture, another architecture currently used in the Itanium server processors. A major hurdle that Intel hinted at will be moving from VLIW to X86 on its 80-core chip.

Although Intel currently has no plans to commercialize the 80-core chip, technologies used in it will definitely be making their way into multi-core desktop chips. So how long until the technologies are expected to finally come to fruition? Intel estimates that it will take 5 – 10 years until we actually begin seeing the benefits of the Tera-scale research project.

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By Operandi on 2/12/2007 2:12:11 PM , Rating: 2
To put this into perspective a quad core Core2 running at the same frequency is capable of how many floating point operations per second?

RE: Perspective
By Tyler 86 on 2/12/2007 4:09:07 PM , Rating: 2
Supposedly 2 Quad Core Xeons (each core being based on Core 2) do between 120 and 210 double-precision GFLOPS... but that's not peak performance, but realizable performance...
I can't find many reliable numbers on it for some reason.

8,000 Opterons + 8,000 Cell processors do >1,000 double-precision TFLOPS, peak...

The R850 (Radeon X1900 core) does 375 GFLOPS, x3 for 1.125 TFLOPS, peak... I think that's double precision, but it can do greater than double precision, and even less than single precision, so I dunno what the full story is with it... but realization of the peak performance is easy with graphics applications.

RE: Perspective
By Tyler 86 on 2/12/2007 4:11:22 PM , Rating: 2
oo.. actually, the 8000 Cell + Opts may be single-precision, uncertain...

RE: Perspective
By Hoser McMoose on 2/12/2007 4:44:42 PM , Rating: 2
Intel's Core architecture contains a 128-bit SSE SIMD engine that can execute one instruction per clock cycle. There is no FMAC instruction though (as this TereFLOP chip uses to get two FLOPS per instruction), only single adds and multiplies. So this gets 4 FLOPs per clock cycle per core.

(Note: All FLOPs here refer to only single-precision FLOPs).

At 3.16GHz a quad core Core2 chip would therefore give:

4 FLOPs/Hz core * 4 cores * 3.16GHz ~= 50GFLOPs.

Surprise, surprise, this chip is actually doing the same number of theoretical FLOPs/Hz core as a Core2 chip is. Actually the only difference is that it does 2 FMACs vs. 4 FAdds or 4 FMult instructions on the Core2.

The Core2 is really a poor chip to compare to though since it is an actual microprocessor while the TereFLOP chip is basically just an FMAC co-processor. A better comparison might be something like the Cell processor, which can manage about 200GFLOPs at 3.2GHz (25GFLOPs per SPE with 8 SPEs in current Cell chips).

Similarly a GeForce 8800 GTX can manage a little more than 520GFLOPs theoretical performance, so a pair of these cards in a system has the same theoretical Linpack performance as Intel's TeraFLOP chip. Of course, in reality these designs are ALL heavily dependent on memory bandwidth and latency. 1 TereFLOP requires at least 4TB/s of memory bandwidth, and that is significantly more than of these solutions are going to provide.

"We don't know how to make a $500 computer that's not a piece of junk." -- Apple CEO Steve Jobs
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