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AMD's internal guidance suggests the company isn't very far from 45nm at all

Late last year, AMD executives alluded to a 45nm successor to the Barcelona core, dubbed Shanghai.  AMD's Senior Vice President, Marty Seyer, claimed Shanghai would specifically "bring further performance enhancements, as well as cache efficiency." 

Shanghai is apparently more than just a cache-bump.  AMD's documentation explicitly claims Shanghai will be the company's first 45nm processor.  However, with a die shrink additional cache is one of the immediate architecture options as the smaller node allows for more transistors to fit on the chip die.  Shanghai features 6MB of L3 cache.

Barcelona, the 65nm quad-core next-generation Opteron from AMD, is expected to launch this summer with 2MB of L3 cache.  L3 cache on the K10 architecture is shared over all four cores, yet each core has an independent L2 cache as well. More details on how this new cache operation works was detailed in June 2006 on DailyTech.

All other features found on Barcelona will also make an appearance on Shanghai: AMD-Virtualization (previously codenamed Presido), RDDR2, and HyperTransport 3.0.  Like Barcelona, Shanghai will also tentatively ship with dual and quad-core variants.  In 2008 AMD will tennatively add Secure Initialization to all its AMD-V platforms, including Shanghai.

Shanghai will also use the Socket 1207 interface, suggesting existing motherboards will have the opportunity to upgrade to Shanghai processors -- AMD processors are typically designed to work with existing motherboards on same-socket interfaces with simple BIOS updates.

AMD and IBM recently announced intentions to pursue the 45nm node with high-k metal gate technology.  Intel disclosed similar process technology information one day prior to the IBM-AMD announcement.  Late last year IBM detailed its plans for utilizing immersion lithography for its 45nm test shuttles -- Intel uses the same process as well.

In a recent interview with Reuters, AMD senior vice president of technology development Douglas Grose claimed "We'll be producing early products probably in Q2 of 2008, with full production in the second half."  However, Grose also claims the company is still anticipating whether or not it will use high-k metal gate technology in later 45nm revisions or if the company will wait until 32nm.

IBM will certainly play an integral role in any 45nm plans for AMD, though production on the 45nm node ramp is not something AMD has discussed at length.  AMD's first 65nm processors just hit store shelves a few weeks ago.

Intel's 45nm processor, codenamed Penryn, has already been taped-out.  Intel guidance suggests the processor will be available to the channel in Q1 2008.

AMD's Barcelona was previously labeled the K8L architecture by AMD President Henri Richard in March 2006. Late last year, AMD executives began using the name K10 instead, while internally the platform is labeled Greyhound.  On paper, Shanghai appears to be architecturally identical to Barcelona, but utilizes the smaller node.


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Facts and BS from IBM
By Lexington on 2/5/2007 11:25:58 PM , Rating: 2
Lets review some the facts here
1) INTEL announced HighK metal gate in 2003
2) They annouced fully functional, 100% yielding 158MegBit arrays in 2006
3) In 2007 they annouced that 45nm would be HighK metal gate and that they had functional CPUs.

IBM has a long history of leadership and publication of their precieved leadership. Look back at all their press about Cu, LowK silk, SOI, etc. etc. Its very odd that this past December they annouced jointly with AMD their 45nm technology without a single mention or hint that HighK was on the roadmap. You would really think that the biggest breakthru in silicon technology would be annouced at the biggest silicon technology conference. Was it, No. Then when they got wind of INTEL's big annouced they did a hasty me to me to.

Look at this statement" We'll be producing early products probably in Q2 of 2008, with full production in the second half." However, Grose also claims the company is still anticipating whether or not it will use high-k metal gate technology in later 45nm revisions or if the company will wait until 32nm. What the hell does "anticipate" mean. Da Grose sure seems to have some interesting work selection that pretty much can be spinned any way you want.

For a seperate look at the circus from IBM go here:
http://www.theregister.co.uk/2007/01/28/intel_ibm_...




RE: Facts and BS from IBM
By ybee on 2/6/2007 12:32:46 AM , Rating: 2
I think if you use SOI you dont really need high k all that much. As far as I remember, high k reduces sub-threshold leakage by increasing oxide capacitance, while SOI does the same by reducing depletion capacitance. So while for Intel high k is critical, for AMD and IBM it may not be as important.

Since high k has its drawbacks - in particular interface trapped charges reduce carrier mobility, IBM and AMD may be actually better off delaying high k introduction till 32nm- even if they have the technology ready for 45nm.



RE: Facts and BS from IBM
By ChipDude on 2/6/2007 11:24:37 AM , Rating: 2
CHeck the latest data on what the gate leakage looks like for atomic layer thick SiON. Gate leakage has become a huge componenet of standby power. SOI does nothing for that.


RE: Facts and BS from IBM
By ybee on 2/6/2007 12:11:48 PM , Rating: 2
Thats right. But the main reason why we want a thin oxide layer is the subthreshold swing, isnt it? With SOI you can probably have a thicker oxide and still get a reasonable swing.

But of course I'm just speculating. I have no idea what are the actual tradeoffs for SOI and high-k for a 45 nm process.


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