Despite the plethora of attention Penryn received
over the last few weeks, Intel's newest roadmaps put the processor launch
for Q1'08. This indicates the launch has not necessarily accelerated even
though the initial
tape-out proved extremely successful.
On the other hand, Intel's 2008 roadmap shows every segment simultaneously
deploying 45nm products. Like AMD's recent 65nm Brisbane
launch, Intel guidance notes the processors will start shipping Q4'07
but the actual launch will come as a coordinated 2008 event.
The first Intel 45nm treatments will come from the quad-core Yorkfield and
dual-core Wolfdale desktop processors. Wolfdale has two
physical cores on a single die and up to 6MB of L2 cache. Yorkfield is then two Wolfdale dice on a single package. Also worth
noting: Wolfdale ships with a 1333MHz front-side bus and Yorkfield ships
with a 1066MHz front-side bus. Chipset support will largely come from Bearlake-family
that was previously
disclosed on DailyTech.
Perhaps the most interesting thing about these two processors is the return of
Hyper-Threading. This, however, does not mean that Yorkfield will
appear as eight logical cores, nor does it mean Wolfdale will appear as
four logical cores. Intel's internal guidance on the subject specifically
claims the processor will ship with Hyper-Threading, but will only utilize 4
threads. On every Intel roadmap in the past, Hyper-Threading doubles the
amount of listed threads in the guidance documentation. Clearly, there is
more of a mystery here still. (Update: Please read the retraction below.)
"The official company policy is that our engineers have left the door open
for Hyper-Threading, but we cannot confirm or deny any future plans for the
technology," adds Intel Public Relations Manager Dan Snyder.
All Penryn cores also include Intel TXT, previously known as Intel LaGrande Technology. TXT stands for Trusted Execution Technology and refers to the collection of devices. The Trusted Platform Module, or TPM, is one component. DMA page protection is another.
Alas, even if 2008 seems like a long time away for the 45nm platform, it's
important to note that all Intel platforms will have 45nm SKUs in Q1'08. Penryn,
the family name for Intel's first generation 45nm consumer CPUs, also refers
specifically to the 45nm dual-core mobile CPU. Intel's current roadmap
claims this processor will lead the Q1'08 mobile push with several low voltage
models coming one quarter later.
For servers, Wolfdale will make an appearance as a dual and single
socket Xeon. It's been long-standing Intel policy to separate desktop,
mobile and server chipsets into different products; Conroe was the Core
2 desktop CPU and Woodcrest, though physically nearly identical, was the
Xeon counterpart. Wolfdale as a server and a desktop CPU indicates
the chips are electrically identical -- though each will likely receive
different packaging for the different sockets.
Yorkfield will not receive the same codenaming treatment as Wolfdale on
the server. Instead, Harpertown will be the quad-core Xeon for two
socket servers. Yorkfield will still be the company’s single-socket
quad-core Xeon offering.
quote: One of the nice things about HT is that it can help hide slow memory, provided you've got enough cache
quote: HT lets you fill in unused issue width with OPs from another thread. So if you stall waiting on a cache miss (or even a cache hit) you can continue to work on another thread rather then letting the CPU grind to a halt for 10-100 clock cycles
quote: True...and in a single core environment this would (and is) usually a very good thing. But the scheduler (and apps) sees the HT virtual core as just another core. So if you are running 2 simultaneous threads, there is no method by which you can direct them to the actual core instead of the virtual core.
quote: I'm sure that you'd agree that only using a single core efficiently instead of splitting the work between 2 cores kind of defeats the purpose of dual (or more significantly quad) core chips.
quote: Ht is useful. Anybody who is computer science in knows that processor parallelism has always been the best road to take when developing a computer
quote: Problem was, Windows didn't know core 1 and core 2 were technically on the same core. So instead of assigning threads to a different core like Core 1 Core 3 THEN core 2 for HT, it crammed in two threads on a loaded processor leaving one unused
quote: To take advantage of this performance opportunity, the scheduler in the Windows Server 2003 family and Windows XP has been modified to identify HT processors and to favor dispatching threads onto inactive physical processors wherever possible.
quote: On a multicore chip, I can't see HT doing very much for performance until CSI and Nehalem is released in 2008/9 (remember that the bottleneck nere is the FSB).
quote: Backup what you are saying.
quote: State how much bandwidth cache coherency traffic takes up on the FSB.
quote: Ummmm....This is K8L we're talking about, not some fanciful chip that's always five years away
quote: where in the article is empirical evidence that the FSB has become saturated or is a bottleneck?
Answer: There isn't any, it's all conjecture
quote: Yeah, prove a negative, that will work
quote: Please point me to this scientific evidence you speak about.
quote: Even though I'm not the one making the statements (you are)
quote: Using Intel analysis tools, running business applications, I see FSB utilization in the 15% percent area on a dual core HP system. Running the same on a quad bumps the utilization to 18%-20%. Business applications run out of cpu long before then run out of FSB bandwidth.