quote: Silly silly silly, have you taken an undergraduate device physics course and understand KT/Q? Vt can't be lowered anymore at room temperature without excessive leakage as you will lower the barrier between source and drain. Anything much lower then 400mV and you can't turn the transistors off. Thus you can't just reduced the drain voltage as Vdd-Vt won't be enough to dry that lowK backend.
Thus to get good drive current and minimum leakage you need Vdd about 1 volt or so. Any lower and you get really low performing transistors. Of course in sleep/slow mode you can do all you want reduce Vdd but then you have this thing called SRAM stability to deal with.
High K / Metal gate is as close to having your cake and eating it to!
quote: SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.
quote: Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.
Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.
quote: I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.