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The first official die shot of "Penryn"

Intel's high-k, metal gate transistors replace the silicon-based elements of the transistor with hafnium and metal composites
Intel confirms new details on "Penryn" family: SSE4, high-k dielectrics, metal gate transistors

A little more than six months ago we wrote an editorial about Intel's future technology after Core 2 Duo, titled "Life After Conroe."  Life after Conroe inches closer, but, in the meantime, more details on the architecture are available today.

DailyTech had the opportunity to chat with Mark Bohr, Intel Senior Fellow, and Steve Smith, Intel Vice President DEG Group Operations, about the upcoming CPU design.

The primary focus of Intel's next-generation process technology is PenrynPenryn is the specific codename a 45nm mobile shrink of the Conroe core, but the codename may also be used to describe the entire product family.  Early last year Intel announced it would optically shrink to the next process node every two years.  Staggered one year later, the company would also announce a new microarchitecture.  This philosophy of shrink followed by architecture revision will undergo its first real milestone with the node shrink from 65nm to 45nm Penryn.  One year after the 45nm Penryn shrink, Intel is also expected to announce its next-generation microarchitecture successor, Nehalem

Intel claims the upcoming Penryn will fit 410 million transistors for the dual-core model, and 820 million transistors for the quad-core variants -- dual-core Conroe utilizes just 298 million transistors.  Intel's 45nm SRAM shuttle chip, announced last year, had a little over 1 billion transistors and fit on a 119mm^2 package.  However, the initial Penryn quad-core processors will use a multi-die packaging, so it's realistic to expect only 410 million transistors per die at launch.

The optical shrink allows the engineers to boost clock speed, but the additional real estate means the company can put more logic on the processor as well. "Most of that transistor savings is spent on increasing the cache over Core 2" added Smith.

Conroe added additional SSE instructions at launch, but Intel claimed at Fall IDF 2006 that SSE4 was specifically reserved for Nehalem.  Intel's guidance for Penryn claims the family will feature "New Intel SSE4 instructions expand capabilities and performance for media/HPC applications."

When asked about the effects of SSE4 on Penryn, Smith responded to DailyTech claiming "We're seeing excellent double digit performance [percentage] gains on multimedia applications."

Penryn is still not without its mysteries; a primary concern for enthusiasts is motherboard and socket support.  Penryn will launch on Socket 775 -- meaning existing motherboards can physically harbor the new CPU,  but electrically might not. "Motherboard developers will have to make some minor changes to support [Penryn]. We can't guarantee that a person could just plug the chip into every motherboard on the market today."  However, Smith also claimed the Penryn boot test that grabbed so many headlines last week occurred on unmodified hardware that included a notebook, several desktop motherboards and several server motherboards.

The lithography process for Penryn, dubbed P1266, is not just a shrink from 65nm to 45nm.  Perhaps the most significant advance on P1266 is the use of high-k dielectrics and metal gate transistors.  In a nutshell, the polysilicon gate used on transistors today is replaced with a metal layer and the silicon dioxide dielectric that sits between the substrate and the transistor is replaced by a high-k dielectric. 

Intel's push for high-k dielectrics and metal gate transistors may be more significant than the node shrink.  Intel's guidance documentation claims with the new high-k dielectric, metal gate transistors offer a 20% increase in current, which can translate to a 20% increase in performance.  When the new transistor technologies run at the same current and frequencies as Core 2 Duo processors today, translates to a 5-fold reduction in source-drain leakage and a 10-fold reduction in dielectric leakage.

"The implementation of high-k and metal gate materials marks the biggest change in transistor technology since the introduction of polysilicongate MOS transistors in the late 1960s" claims Gordon Moore, Intel co-founder attributed with coining "Moore's Law."

Intel would not reveal the materials used in its metal gate technology, though Smith announced that the dielectric is hafnium based.  Hafnium dioxide has been the leading candidate to replace silicon oxide inside academia for years.  A different material is used for PMOS and NMOS gates.

Intel's lithography roadmap no longer ends at P1268, the 32nm node.  Earlier today Intel revealed its 22nm node, dubbed 1270, slated for first production in 2011. 

Smith closed our conversation with "In 2008, we'll have Nehalem."

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RE: This is pretty funny
By ChipDude on 1/27/2007 11:45:02 PM , Rating: 2
Hi K is absolutly NOT in AMD's 65nm. AMD is using the same old boring nitrided oxide they used in previous generations.

AMD/IBM have already stated they are NOT using HiK in their 65nm. All they could do was lower the K a bit for the backend and throw immersion in because they couldn't figure out how to pattern with 193nm dry.

RE: This is pretty funny
By flipsu5 on 1/28/2007 2:34:17 AM , Rating: 2
Immersion is only in their 45 nm. It's the other way around. Intel is not doing immersion because they do not have the tools in time for ramp.

Both AMD and Intel were prepared to do 45 nm with or without high-k.

The only barrier to doing BOTH immersion and high-k is purely cost of two dramatic changes at once, since you would need new hardware for both processes.

RE: This is pretty funny
By Viditor on 1/30/2007 3:40:21 AM , Rating: 1
Remember also that there is a difference between the 2 HK/MG processes here...
Unlike Intel, IBM has figured out how to embed its new metal gates directly into silicon (Intel's gates must still sit atop a silicon architecture structure).
This will be even more important as they shrink to 32nm and 22nm...

RE: This is pretty funny
By ChipDude on 1/30/2007 11:19:58 AM , Rating: 2
Another brilliant technologist.

Tell me if you embed the gate in the silicon how it acts like a gate. Do you know what MOS transistor stands for?

Metal on Oxide on Silicon = MOS

Now INTEL has put real metal on top of an Oxide ( HiK ) on silicon to form a MOS transistor.

Putting Metal in the silicon causes nasty things, degraded lifetime, high junction leakage etc. etc.

RE: This is pretty funny
By Viditor on 1/30/2007 7:32:06 PM , Rating: 2
Another EE student who's forgotten how to read articles...

Intel's manufacturing lead should allow it to bring chips to market before its rivals, but IBM could get a greater return from this technology in the long term because it uses the high-k metal gates in a different way, one analyst said. "It's a wonderfully parallel development of a technology that should lead to faster, more efficient chips in everything from PCs to cell phones and iPods," said Richard Doherty, senior analyst with The Envisioneering Group.

"Intel has the advantage that they're already in production, but IBM's advance may be even more significant and lead to faster, smaller chips. The IBM breakthrough is to integrate the metal gate so it's embedded in the silicon. Intel put the metal gates on top of a proven silicon architecture."

RE: This is pretty funny
By Khato on 1/30/2007 8:12:27 PM , Rating: 2
AMD plans to produce its first 45nm chips in mid-2008, in the wake of the launch of its first 65nm product, the quadcore "Barcelona", due out in mid-2007.

Reading some articles is indeed rather humorous. Anyway, quotes from analysts don't tend to mean much to me. Far more interesting is to look at the IBM research paper on the matter that the register posted up:

Their 'embedded in the silicon' is actually a conventional poly-Si deposited over the metal gate, something that really -should- be quite unnecessary. Anyway, what I love about the paper is the info on their HK/MG pFET devices, the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is.

RE: This is pretty funny
By Viditor on 1/30/2007 8:54:34 PM , Rating: 2
quotes from analysts don't tend to mean much to me

Fair enough...and thanks for the link!
the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is

I believe that East Fishkill has already been converted to HK/MG...the key is that the IBM conversion appear to be a much simpler process...

"We don't build Vespa scooters, we build Ferraris. We've been talking about high-k for five years now, and if we wanted to, we could ship it out the door tomorrow. But there's no reason to do that because it doesn't solve any problem for us. We're not addressing a crisis issue that hit us in the head when we didn't see it coming," Meyerson said.

"Ours is a more fundamental implementation; it's a drop-in, or a one-for-one replacement, for SiO2 ," he said, referring to existing silicon dioxide technology. "I've said for years that gate oxide scaling is ending. The gates are literally five atoms thick. What are you going to do, build one that's two-and-a-half atoms thick?"

The interesting questions for me are
1. What is Intel's goal/need for HK/MG? (meaning from a marketing or performance standpoint)
2. How will ultra-low k connects compare to Intel's process and what will that mean for marketing/performance?

RE: This is pretty funny
By Khato on 1/31/2007 1:41:50 AM , Rating: 2
Yay, yes, the quote from the engineer was the highlight of that little article =D Granted, he has the typical bias towards his company, but, don't we all? Anyway, my little comment on the bolded portion is that it can't be a one for one replacement of SiO2 with HfO2, since there are problems with using Poly-Silicon directly on the halfnium oxide (it'll work, but not near so well as with metal gate.) But, eh, they don't get into enough detail to say how it's 'drop in'.

1. I would assume it's more a marketing point - performance per watt. True, the average consumer doesn't care as much about it. But system integrators love it for easing the cost of cooling designs. And it has fast become -the- metric in many server applications. So what if server X outperforms server Y by a small amount if two X's consume the same amount of energy as one Y?

2. That is indeed an interesting query. Heh, at the current dimensions interconnects are getting to be far more of a factor, no question. Still, on Intel's 45nm info page, they have the interesting little statement of, "Approximately 30 percent reduction in transistor-switching power." This is indeed a tad bit vague, if in comparison to 65nm, the majority could be due to voltage decrease. But, the remaining amount would be due to reduced capacitances, and I would guess that amount is at least as much as what the ultra low-k interconnect dielectrics would offer.

RE: This is pretty funny
By Viditor on 1/31/2007 7:24:38 AM , Rating: 2
they don't get into enough detail to say how it's 'drop in'

This is well over my head, but the link you provided says:

Short channel HK/MG devices were fabricated from <20Å HfO2 with
thermally stable BE metal gates in a gate-first approach where
conventional poly-Si is deposited over the metal gates. Following a
lithographic patterning and gate stack etch process, a conventional selfaligned
implant process flow with a final S/D spike RTA (T>1080°C) +
advanced annealing (AA) and dual stress liner (DSL) with conventional
MOL and BEOL was used

Does that help? :)

RE: This is pretty funny
By Khato on 1/31/2007 11:39:38 AM , Rating: 2
I'll freely admit that I shied away from the 8000 level semiconductor properties course after having gotten through the 5000 level one, so I don't understand quite everything either, lol.

What I find mildly confusing about all the stuff IBM has said is that they're being rather mute on a change to metal gate electrodes. Technically, they'd have a high-k metal gate by simply using hafnium as the gate dielectric and continuing to use poly-Si for the gate electrode. (After all, hafnium is a transition metal.) I'd hope it's simply the press releases dumbing it down that make it seem as such. But the fact that the paper lacks any mention of a metal gate electrode and -does- say that poly-Si is deposited over the metal gates is a tad bit worrysome. Maybe they'll have further information in time, just seems odd that they're not mentioning anything about the gate electrodes really.

RE: This is pretty funny
By flipsu5 on 2/6/2007 11:30:27 PM , Rating: 2
Some more details are reported in another paper at the 2004 VLSI symposium on VLSI Technology "Thermally robust dual-work function ALD-MNx MOSFETs using conventional CMOS process flow".

The metal gate (TaN for N, WN for P) is thin (~10 nm) and deposited by ALD. The polysilicon is needed to be on top to enhance the thermal stability. I also know it shields the gate dielectric better from lithography radiation; the metal is too thin.

"Intel is investing heavily (think gazillions of dollars and bazillions of engineering man hours) in resources to create an Intel host controllers spec in order to speed time to market of the USB 3.0 technology." -- Intel blogger Nick Knupffer
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