HP Boasts Enormous Transistor Densities Gains with Nanowire Interconnects
January 17, 2007 1:42 AM
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New nanotechnology procedures from HP may become the norm for processor design as early as 2010
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HP Lab Researchers have created a new “field programmable nanowire interconnect" (FPNI) architecture, a variation on the FPGA technology, that could allow chip makers to place eight times the number of transistors currently possible on standard 45nm field programmable gate array, or FPGA, chips.
Stan Williams, an HP Senior Fellow and director,
said in a press statement
“As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics. Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
Current conventional FPGA chips use 80 to 90 percent of their CMOS for signal routing, leaving a relatively small portion for logic processing transistors. With the new FPNI approach, all logic operations will be performed in the CMOS (complementary metal oxide silicon) while most of the signal routing will take place in a nanoscale crossbar switch structure which will be placed on top of the CMOS.
The crossbar is connected to the CMOS using technology developed by Dmitri Strukov and Konstantin Likharev of Stony Brook University in New York. The new FPNI approach is said to have numerous benefits including the possibility of a much higher transistor count along with lower power consumption.
The first implementation of the new method, which uses 15-nanometer-wide crossbar wires combined with 45nm half-pitch CMOS on a conservative chip model, is said to be the equivalent of a three generation leap on the International Technology Roadmap for Silicon without having to shrink the transistors. Restating it, this means that applying the FPNI architecture using a 15nm crossbar on a current 45nm chip will allow 8 times as many transistors compared to using no crossbar. Researchers believe this model will be technologically possible by 2010.
A model based on 4.5nm-wide crossbar architecture combined with 45nm CMOS was also presented. The 4.5nm-wide crossbar would allow the same amount of transistors to be placed in a hybrid chip only 4 percent the size of a current 45nm chip. Snider and Williams believe it will be ready by 2020.
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RE: by 2010
1/17/2007 3:27:30 PM
These babies might sit on your PCI-E 3.0 add on card and be upgradable by flash helping your system with what your system does most. Sure they have a future.
“Then they pop up and say ‘Hello, surprise! Give us your money or we will shut you down!' Screw them. Seriously, screw them. You can quote me on that.” -- Newegg Chief Legal Officer Lee Cheng referencing patent trolls
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