NEC Electronics, working jointly with Elpida Memory and Oki
Electric, says it has developed novel packaging technology that places eight
memory chips and one controller chip in a vertical stack, with 3D connections
between the chips.
The key feature of the new technology is the way that chips
in the stack are connected. Each chip has more than 1,000 pins on each side.
The pins are connected to polysilicon electrodes built into the chips
themselves, vertically piercing the chips from top to bottom. The chips are
then connected to each other by high-density microbumps spaced only 50
micrometers apart. The entire package, including the controller chip, is very
compact because each of the eight memory chips is only 50 micrometers thick.
For applications like digital video and 3D games, mobile
devices also need faster access to memory and power consumption as low as
possible. Chip suppliers have developed a number of ways to meet these requirements.
Memory can be built into system-on-chip solutions, or included in
The latter approach typically involves stacking a
number of memory chips over interposers and connecting them to a processor chip
by wire bonding. But each of these approaches has its disadvantages. It is
difficult to build enough memory into a single SoC chip. The wire bonding in
SiP solutions creates impedance balancing problems and limits the number of
pins that can be connected to the processor, which makes it difficult to
increase the signal speed. Wire bonding also limits the number of chips that
can be added to the stack.
In search of a fundamental solution to these problems, NEC/Elpida/Oki
engineers focused on packaging technology to allow stacking of eight memory
chips and one controller chip with internal microbump connections at the dense
pitch of 50 µm. This technology will enable smaller form factors, faster
operating speeds and lower power consumption in the next generation of mobile
Samsung is also developing its own stacked memory technology
for flash applications. Reportedly, Samsung is working to increase flash memory
sizes up into the terabit range, which would greatly expand the capacity of all
portable media devices. Read this article from Technology Review on Samsung’s
presentation on 3D memory at International Electron Device meeting in San
Francisco last week.