Over the last few months much as been revealed about AMD's
next-generation quad-core architecture. This architecture, previously
dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core
design. AMD engineers still internally refer to this architecture as Greyhound.
Since unveiling the details of the chip, AMD has started to use the codename Barcelona
to describe the server variant. The Barcelona chipset is a member of
the Cities family -- all server-based AMD codenames for 2007 and 2008
are named after Cities. Desktop codenames are all named after Stars
even though architecturally, many Stars and Cities CPUs are
AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced"
with the Shanghai core in early 2008. AMD's Senior
Vice President, Marty Seyer, would not elaborate on what the enhancements are,
claiming that the new core would simply "bring further performance enhancements,
as well as cache efficiency."
When the Greyhound architecture was publically unveiled this past June, AMD's
Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona
processor would utilize 2MB of L3 shared cache -- hinting that additional
versions of K10 with larger caches are roadmap possibilities. Although we
cannot speak for the other enhancements, the additional cache Hester described
in June 2006 is almost certainly present in Shanghai.
As with previous generations of Opteron processors, Barcelona will only
encompass the multi-socket codename. For single-socket servers, Budapest will
act as AMD's city codename for the 1xxx Opteron processor. There is no
"cache-upgrade" version of Budapest in the way that Shanghai is an
upgrade for Barcelona. This is likely due to the fact that whatever enhancements
are on Shanghai do not necessarily show performance gains on single-socket
According to AMD's roadmaps, Shanghai will still utilize DDR2 memory,
though DDR3 processors are also slated for production around that time as
well. "DDR2 is going to serve us quite nicely for several
years," added Seyer.
quote: And no one puts tons of cache on chips "because they can". The[y] do it because they HAVE to. Cache takes up die space, and space eats into margins. If they didn't need the cache, they'd use that extra space to make more CPUs from each wafer, meaning they could sell each one cheaper, and regain market share faster.