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AMD executives reveal more cache, more quad-core en route for AMD

Over the last few months much as been revealed about AMD's next-generation quad-core architecture.  This architecture, previously dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core design. AMD engineers still internally refer to this architecture as Greyhound.

Since unveiling the details of the chip, AMD has started to use the codename Barcelona to describe the server variant. The Barcelona chipset is a member of the Cities family -- all server-based AMD codenames for 2007 and 2008 are named after Cities. Desktop codenames are all named after Stars even though architecturally, many Stars and Cities CPUs are identical.

AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced" with the Shanghai core in early 2008.  AMD's Senior Vice President, Marty Seyer, would not elaborate on what the enhancements are, claiming that the new core would simply "bring further performance enhancements, as well as cache efficiency." 

When the Greyhound architecture was publically unveiled this past June, AMD's Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K10 with larger caches are roadmap possibilities. Although we cannot speak for the other enhancements, the additional cache Hester described in June 2006 is almost certainly present in Shanghai.

As with previous generations of Opteron processors, Barcelona will only encompass the multi-socket codename. For single-socket servers, Budapest will act as AMD's city codename for the 1xxx Opteron processor.  There is no "cache-upgrade" version of Budapest in the way that Shanghai is an upgrade for Barcelona.  This is likely due to the fact that whatever enhancements are on Shanghai do not necessarily show performance gains on single-socket systems.

According to AMD's roadmaps, Shanghai will still utilize DDR2 memory, though DDR3 processors are also slated for production around that time as well.  "DDR2 is going to serve us quite nicely for several years," added Seyer.



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RE: This is for AMD
By sbandyk on 12/16/2006 10:20:05 PM , Rating: 2
quote:
And no one puts tons of cache on chips "because they can". The[y] do it because they HAVE to. Cache takes up die space, and space eats into margins. If they didn't need the cache, they'd use that extra space to make more CPUs from each wafer, meaning they could sell each one cheaper, and regain market share faster.


Who says? You put exactly what you need to on a chip to hit your performance target. If it's not cache, it's a memory controller or more registers or another core.
You also put in the ammount of cache that maximizes returns. If 4 MB of CACHE gets you 5% better performance than 1MB of CACHE Intel would never run 4MB of CACHE.

I see what you're trying to say.. Intel is cheating because they HAVE TO put more cache on. That smacks as a pretty bold assertion without support. They put more cache on because it pays dividends in performanace. They also put more cache in because they make their performace targets (that is.. currently faster than AMD).
By your reasoning.. no one puts an Integrated Memory controller on because they want to.. they do it because they HAVE to. How about this.. No one adds more SSE instructions or 64bit instruction extensions because they want to, they do it because they HAVE to.

BTW.. as for price being the way to market share.. It was Intel that forced the latest price war. The price/performance on the Core2 chips is fantastic IMHO. The last time I saw a Fry's budget combo it was a P4 Dual-Core and MB for $120. I wouldn't buy one for games (or Fluid Dynamics) but it's a hell of a lot of computer for that cheap. I walked in expecting a Semperon bundle for just a bit less.

One other thing I need to comment on, IMCs are great when you've got A processor. Personally, I dislike the IMCs because I work in the IT industry and I deal with more than one personal computer a year (like an enthusiast). I'm currently shopping for, preferably, 8 cores in some new computational nodes. I can go 4CPU Dual-Core Opteron and pay an arm and a leg and I've got to purchase my memory 8 DIMMs at a time. At the very least, It's much more difficult to buy now, upgrade later.
With Intel, I can get my 2-cpu quad-core nodes and save money on memory now [just enough] until I line up more funding. I'm also get to upgrade the system pool of memory and not per physical CPU.
AMD's reliance on IMC has also held AMD back. They've been slow to adapt to architctual changes in memory because moving to a new memory standard will always require a redesign of the CPU and possibly the socket. AMD will have to deal with this all over again for DDR-3. In the move to DDR-2 this wasn't initially a big deal since DDR2 latency was higher and Athlon64's low latency IMC is really THE performance feature (topping off an all around strong processor). AMD's delay in moving to AM2 and DDR2 is a liability now however. DDR prices are up, DDR2 prices are down and the speed and real and functional latency is down on the DDR2 chips (faster clocked DDR2 has lower effective latency in real time and lower latence chips at any given speed are now available).
Unfortunately, what we have now are more AMD DDR systems that aren't that old but they require increasingly expensive, increasingly obsolete memory. DDR and DDR2 prices are nearly the same if you look at memory that is common now (ddr400 v. ddr2-667)

Overall, I'm very happy with Intel's current products and their roadmap. I'd like to see a higher performance interconnect, especially on the high end smp boxes but I can't argue with the performance or the price. I'm looking at ready to deploy, warrantied single vendor 8-core computational nodes in the $7K USD range and that's not with the low end cpus. I'll likely go 2.33GHz because our chiller is a problem but I could go top of the line and still keep it under 8K with a real server warranty.. or I could go 4xdual Opteron for about $10K with a similar config...

What was that about cutting a little cache to win on price?

P.S. Would Intel actually have to license HT? HyperTransport is the product of an industry consortium, hell even Apple is a member of the HT design committee. Intel has co-opted AMD's 64bit extensions, I'd assume they have other reasons for not using a per-cpu serial link by now.


RE: This is for AMD
By crystal clear on 12/17/2006 12:21:47 AM , Rating: 2
QUOTE-
"P.S. Would Intel actually have to license HT? HyperTransport is the product of an industry consortium, hell even Apple is a member of the HT design committee. Intel has co-opted AMD's 64bit extensions, I'd assume they have other reasons for not using a per-cpu serial link by now."

UNQUOTE-If INTEL GAVE THE TICK-TOCK YOU GAVE THE " GONG "


RE: This is for AMD
By Justin Case on 12/17/2006 5:52:52 PM , Rating: 2
Was that a rethorical question or something? Of course Intel would have to license HT. They're not members of the HT consortium. Just as AMD had to license some DDR3 / PCIe patents (from RAMBUS) for their next-generation chips.

HT has nothing to do with x86 and is not covered by the AMD-Intel instruction set agreement.

And trust me, if the chips performed well enough with lower cache (say, only 5% slower with half the cache), they wouldn't even think twice about reducing it and using the extra space to get more dies out of each wafer. It's simple economics. They need the extra cache because their interconnects are too slow to keep the cores fed, and there is no other short-term solution (other than selling much slower chips, and that wouldn't look good).

No one adds stuff to a chip (especially something like cache, that takes up a lot of space) unless it's _necessary_. Die area and profit margins go hand in hand (for more than one reason). If you don't realise that, you clearly don't work in this industry.




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