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AMD executives reveal more cache, more quad-core en route for AMD

Over the last few months much as been revealed about AMD's next-generation quad-core architecture.  This architecture, previously dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core design. AMD engineers still internally refer to this architecture as Greyhound.

Since unveiling the details of the chip, AMD has started to use the codename Barcelona to describe the server variant. The Barcelona chipset is a member of the Cities family -- all server-based AMD codenames for 2007 and 2008 are named after Cities. Desktop codenames are all named after Stars even though architecturally, many Stars and Cities CPUs are identical.

AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced" with the Shanghai core in early 2008.  AMD's Senior Vice President, Marty Seyer, would not elaborate on what the enhancements are, claiming that the new core would simply "bring further performance enhancements, as well as cache efficiency." 

When the Greyhound architecture was publically unveiled this past June, AMD's Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K10 with larger caches are roadmap possibilities. Although we cannot speak for the other enhancements, the additional cache Hester described in June 2006 is almost certainly present in Shanghai.

As with previous generations of Opteron processors, Barcelona will only encompass the multi-socket codename. For single-socket servers, Budapest will act as AMD's city codename for the 1xxx Opteron processor.  There is no "cache-upgrade" version of Budapest in the way that Shanghai is an upgrade for Barcelona.  This is likely due to the fact that whatever enhancements are on Shanghai do not necessarily show performance gains on single-socket systems.

According to AMD's roadmaps, Shanghai will still utilize DDR2 memory, though DDR3 processors are also slated for production around that time as well.  "DDR2 is going to serve us quite nicely for several years," added Seyer.

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RE: This is for AMD
By coldpower27 on 12/16/2006 9:55:56 PM , Rating: 2
No they can't as that is too risky a change, they made some changes to architecture with the Core to Core 2 leap. They will address the interconnects with Nehalem, they are doing things one step at a time. Prescott did too many changes at once and turned out poorly, though still an adequate product. They learned their lesson and will just take things in a proper step by step manner.

Yes, Intel does because they can afford it, they are not strapped for production capacity like AMD, cache does take up some die space, but not enough to be seriously detrimental to someone with Intel's resource levels as well as expertise on cache technology. There is also the issue of selling their chips for higher margins, they can charge more for the higher cache versions. They have always been able to afford to put larger amounts of cache of their processors, hell they disable the full cache size versions to create lower SKU without the need to make another processor with a native reduced cache size to address each market. Intel produces cache amounts it can easily afford to produce in quantity for each market segment.

The IMC itself on AMD's architecture takes up quite a bit of real estate on AMD's processor, they do it because it provides significant performance enhancements. They also don't like to rely on cache as like I said for AMD it takes up a significant real estate on the die, probably as much or more then the IMC and provides less of a gain.

AMD's architecture only has an advantage on the server front, when competing with NetBurst derivatives, The only remaining bastion right now for AMD is the Opteron 8xxx, line the Woodcrest is more then enough to compete against the Opteron 2xxx even using legacy FSB technology.

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