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AMD executives reveal more cache, more quad-core en route for AMD

Over the last few months much as been revealed about AMD's next-generation quad-core architecture.  This architecture, previously dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core design. AMD engineers still internally refer to this architecture as Greyhound.

Since unveiling the details of the chip, AMD has started to use the codename Barcelona to describe the server variant. The Barcelona chipset is a member of the Cities family -- all server-based AMD codenames for 2007 and 2008 are named after Cities. Desktop codenames are all named after Stars even though architecturally, many Stars and Cities CPUs are identical.

AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced" with the Shanghai core in early 2008.  AMD's Senior Vice President, Marty Seyer, would not elaborate on what the enhancements are, claiming that the new core would simply "bring further performance enhancements, as well as cache efficiency." 

When the Greyhound architecture was publically unveiled this past June, AMD's Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K10 with larger caches are roadmap possibilities. Although we cannot speak for the other enhancements, the additional cache Hester described in June 2006 is almost certainly present in Shanghai.

As with previous generations of Opteron processors, Barcelona will only encompass the multi-socket codename. For single-socket servers, Budapest will act as AMD's city codename for the 1xxx Opteron processor.  There is no "cache-upgrade" version of Budapest in the way that Shanghai is an upgrade for Barcelona.  This is likely due to the fact that whatever enhancements are on Shanghai do not necessarily show performance gains on single-socket systems.

According to AMD's roadmaps, Shanghai will still utilize DDR2 memory, though DDR3 processors are also slated for production around that time as well.  "DDR2 is going to serve us quite nicely for several years," added Seyer.



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RE: This is for AMD
By Targon on 12/16/2006 7:30:45 AM , Rating: 1
While Intel may be ahead when it comes to process technology, we still see Intel using their old system design, which has been a huge bottleneck for them. They NEED to put crazy amounts of cache on their processors in order to compete(P4 generation) and stay ahead(Core generation).

AMD may be behind in terms of manufacturing process technology, but are pulling ahead in terms of system architecture improvements.

Historically, Intel is able to use their resources to push the current designs further. In the MHz race, Intel pushed and pushed and pushed. Now they are pushing on process technology. Notice that since the release of the original Athlon, AMD has managed to compete, and for a long time were able to beat the best that Intel had to show. There WILL be a limit to how far process technology can shrink, and that may be what eventually kills Intel.



RE: This is for AMD
By coldpower27 on 12/16/2006 8:53:40 AM , Rating: 2
They can't address everything at once, system interconnect improvements are slated for the Nehalem.

They are putting crazy amounts of cache (in comparison to AMD) because their cache expertise is great, they can fit dramatically more cache on a given area then AMD can, not to mention it's faster. They also have the manufacturing muscle to afford larger amounts of cache then AMD as they are production limited. One of the reason AMD's decided to go IMC, was that they knew they weren't quite as good on cache technology, and wanted it's effects minimized. Hence adding more cache to K8 derivatives produces limited gains.

The only reason that AMD Athlon was able to pull ahead, was that Intel let their marketeers take control of design instead of build a proper performance oriented design. Once Intel is taking the architecture race seriously, it is likely this tick tock mechanism, will keep them inline and competitive, short of a major mistake. It's unlikely you will see something like the Athlon 64x2 vs the Pentium D situation again.


RE: This is for AMD
By Justin Case on 12/16/2006 12:12:38 PM , Rating: 2
Of course they could address everything at once. The people working on architecture design aren't the same people who are working on manufacturing process technology.

And no one puts tons of cache on chips "because they can". The do it because they HAVE to. Cache takes up die space, and space eats into margins. If they didn't need the cache, they'd use that extra space to make more CPUs from each wafer, meaning they could sell each one cheaper, and regain market share faster.

The problem with Intel is that it suffers from a very nasty "not invented here" syndrome. The whole P4 fiasco was caused by the fact that a) Intel refused to adopt innovations created by AMD and b) Intel USA refused to let an Israeli-developed architecture (the Pentium-M / Core Duo) be their flagship product. Anyone with a clue could see the Pentium-M was a much better design than the P4; add AMD64 instructions and multi-core and you'd have a winner (aka Core 2 Duo).

Eventually Intel's profits and their market share dropped so much that they were forced to come to their senses. And, from a consumer's point of view, I only wish that had happened sooner (not only because the new Intel chips are faster, but also because it forces AMD to drop their prices).

Now, Intel is still far behind AMD in terms of interconnects. AMD has hired a lot of key people (some from Intel, no less) in areas related to memory bandwidth and co-processor architectures, and the AMD-led HyperTransport consortium unites nearly every major IC manufacturer except Intel.

Will Intel bite yet another bullet and license HT, or will they stick to their bus-based design until they have CSI ready? Waiting could cost them a lot on the server front (where AMD still has the advantage, despite being one CPU generation and one manufacturing process generation behind - all thanks to their superior interconnect technology).



RE: This is for AMD
By coldpower27 on 12/16/2006 9:55:56 PM , Rating: 2
No they can't as that is too risky a change, they made some changes to architecture with the Core to Core 2 leap. They will address the interconnects with Nehalem, they are doing things one step at a time. Prescott did too many changes at once and turned out poorly, though still an adequate product. They learned their lesson and will just take things in a proper step by step manner.

Yes, Intel does because they can afford it, they are not strapped for production capacity like AMD, cache does take up some die space, but not enough to be seriously detrimental to someone with Intel's resource levels as well as expertise on cache technology. There is also the issue of selling their chips for higher margins, they can charge more for the higher cache versions. They have always been able to afford to put larger amounts of cache of their processors, hell they disable the full cache size versions to create lower SKU without the need to make another processor with a native reduced cache size to address each market. Intel produces cache amounts it can easily afford to produce in quantity for each market segment.

The IMC itself on AMD's architecture takes up quite a bit of real estate on AMD's processor, they do it because it provides significant performance enhancements. They also don't like to rely on cache as like I said for AMD it takes up a significant real estate on the die, probably as much or more then the IMC and provides less of a gain.

AMD's architecture only has an advantage on the server front, when competing with NetBurst derivatives, The only remaining bastion right now for AMD is the Opteron 8xxx, line the Woodcrest is more then enough to compete against the Opteron 2xxx even using legacy FSB technology.


RE: This is for AMD
By sbandyk on 12/16/2006 10:20:05 PM , Rating: 2
quote:
And no one puts tons of cache on chips "because they can". The[y] do it because they HAVE to. Cache takes up die space, and space eats into margins. If they didn't need the cache, they'd use that extra space to make more CPUs from each wafer, meaning they could sell each one cheaper, and regain market share faster.


Who says? You put exactly what you need to on a chip to hit your performance target. If it's not cache, it's a memory controller or more registers or another core.
You also put in the ammount of cache that maximizes returns. If 4 MB of CACHE gets you 5% better performance than 1MB of CACHE Intel would never run 4MB of CACHE.

I see what you're trying to say.. Intel is cheating because they HAVE TO put more cache on. That smacks as a pretty bold assertion without support. They put more cache on because it pays dividends in performanace. They also put more cache in because they make their performace targets (that is.. currently faster than AMD).
By your reasoning.. no one puts an Integrated Memory controller on because they want to.. they do it because they HAVE to. How about this.. No one adds more SSE instructions or 64bit instruction extensions because they want to, they do it because they HAVE to.

BTW.. as for price being the way to market share.. It was Intel that forced the latest price war. The price/performance on the Core2 chips is fantastic IMHO. The last time I saw a Fry's budget combo it was a P4 Dual-Core and MB for $120. I wouldn't buy one for games (or Fluid Dynamics) but it's a hell of a lot of computer for that cheap. I walked in expecting a Semperon bundle for just a bit less.

One other thing I need to comment on, IMCs are great when you've got A processor. Personally, I dislike the IMCs because I work in the IT industry and I deal with more than one personal computer a year (like an enthusiast). I'm currently shopping for, preferably, 8 cores in some new computational nodes. I can go 4CPU Dual-Core Opteron and pay an arm and a leg and I've got to purchase my memory 8 DIMMs at a time. At the very least, It's much more difficult to buy now, upgrade later.
With Intel, I can get my 2-cpu quad-core nodes and save money on memory now [just enough] until I line up more funding. I'm also get to upgrade the system pool of memory and not per physical CPU.
AMD's reliance on IMC has also held AMD back. They've been slow to adapt to architctual changes in memory because moving to a new memory standard will always require a redesign of the CPU and possibly the socket. AMD will have to deal with this all over again for DDR-3. In the move to DDR-2 this wasn't initially a big deal since DDR2 latency was higher and Athlon64's low latency IMC is really THE performance feature (topping off an all around strong processor). AMD's delay in moving to AM2 and DDR2 is a liability now however. DDR prices are up, DDR2 prices are down and the speed and real and functional latency is down on the DDR2 chips (faster clocked DDR2 has lower effective latency in real time and lower latence chips at any given speed are now available).
Unfortunately, what we have now are more AMD DDR systems that aren't that old but they require increasingly expensive, increasingly obsolete memory. DDR and DDR2 prices are nearly the same if you look at memory that is common now (ddr400 v. ddr2-667)

Overall, I'm very happy with Intel's current products and their roadmap. I'd like to see a higher performance interconnect, especially on the high end smp boxes but I can't argue with the performance or the price. I'm looking at ready to deploy, warrantied single vendor 8-core computational nodes in the $7K USD range and that's not with the low end cpus. I'll likely go 2.33GHz because our chiller is a problem but I could go top of the line and still keep it under 8K with a real server warranty.. or I could go 4xdual Opteron for about $10K with a similar config...

What was that about cutting a little cache to win on price?

P.S. Would Intel actually have to license HT? HyperTransport is the product of an industry consortium, hell even Apple is a member of the HT design committee. Intel has co-opted AMD's 64bit extensions, I'd assume they have other reasons for not using a per-cpu serial link by now.


RE: This is for AMD
By crystal clear on 12/17/2006 12:21:47 AM , Rating: 2
QUOTE-
"P.S. Would Intel actually have to license HT? HyperTransport is the product of an industry consortium, hell even Apple is a member of the HT design committee. Intel has co-opted AMD's 64bit extensions, I'd assume they have other reasons for not using a per-cpu serial link by now."

UNQUOTE-If INTEL GAVE THE TICK-TOCK YOU GAVE THE " GONG "


RE: This is for AMD
By Justin Case on 12/17/2006 5:52:52 PM , Rating: 2
Was that a rethorical question or something? Of course Intel would have to license HT. They're not members of the HT consortium. Just as AMD had to license some DDR3 / PCIe patents (from RAMBUS) for their next-generation chips.

HT has nothing to do with x86 and is not covered by the AMD-Intel instruction set agreement.

And trust me, if the chips performed well enough with lower cache (say, only 5% slower with half the cache), they wouldn't even think twice about reducing it and using the extra space to get more dies out of each wafer. It's simple economics. They need the extra cache because their interconnects are too slow to keep the cores fed, and there is no other short-term solution (other than selling much slower chips, and that wouldn't look good).

No one adds stuff to a chip (especially something like cache, that takes up a lot of space) unless it's _necessary_. Die area and profit margins go hand in hand (for more than one reason). If you don't realise that, you clearly don't work in this industry.




RE: This is for AMD
By crystal clear on 12/17/2006 12:45:22 AM , Rating: 2
Quote-

"Intel USA refused to let an Israeli-developed architecture (the Pentium-M / Core Duo) be their flagship product."

Unquote-

There are some more CORE surprises on the way in a Tick Tock
fashion from Intel(Israel).


RE: This is for AMD
By Justin Case on 12/17/2006 5:54:42 PM , Rating: 2
Exactly. Can you imagine how much better things would be (for Intel and for consumers) if Intel hadn't spent three years whacking the P-M on the head while it tried to flog the dead horse (P4)?


RE: This is for AMD
By carl0ski on 12/20/2006 9:13:13 PM , Rating: 2
i always felt the IMC by AMD was largely due to the fact

AMD no longer maae a northbridge Chipset and the memory performance was at the mercy of
VIA & SIS development

between mainboards and chipsets
AMD K7 memory performance and stability varied radically causing poor performance tag and public confusion especially in the low-mid range.



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