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AMD executives reveal more cache, more quad-core en route for AMD

Over the last few months much as been revealed about AMD's next-generation quad-core architecture.  This architecture, previously dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core design. AMD engineers still internally refer to this architecture as Greyhound.

Since unveiling the details of the chip, AMD has started to use the codename Barcelona to describe the server variant. The Barcelona chipset is a member of the Cities family -- all server-based AMD codenames for 2007 and 2008 are named after Cities. Desktop codenames are all named after Stars even though architecturally, many Stars and Cities CPUs are identical.

AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced" with the Shanghai core in early 2008.  AMD's Senior Vice President, Marty Seyer, would not elaborate on what the enhancements are, claiming that the new core would simply "bring further performance enhancements, as well as cache efficiency." 

When the Greyhound architecture was publically unveiled this past June, AMD's Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K10 with larger caches are roadmap possibilities. Although we cannot speak for the other enhancements, the additional cache Hester described in June 2006 is almost certainly present in Shanghai.

As with previous generations of Opteron processors, Barcelona will only encompass the multi-socket codename. For single-socket servers, Budapest will act as AMD's city codename for the 1xxx Opteron processor.  There is no "cache-upgrade" version of Budapest in the way that Shanghai is an upgrade for Barcelona.  This is likely due to the fact that whatever enhancements are on Shanghai do not necessarily show performance gains on single-socket systems.

According to AMD's roadmaps, Shanghai will still utilize DDR2 memory, though DDR3 processors are also slated for production around that time as well.  "DDR2 is going to serve us quite nicely for several years," added Seyer.

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45nm, DDR3 or Z-RAM ??
By Xajel on 12/15/2006 12:11:07 AM , Rating: 2
will the Shaghi be the 45nm part ??

I think - as AMD stated about going for more cache - they will trasit to 45nm part earlier than mid08 ( in 1H ), and after that, they will bring DDR3 with AM3 in mid08..

what this cache is it that Z-RAM thing ??
so the 2MB L3 cache may be magicly increased to 10MB !! naaaa I don't think that much but it's logical you know, same silicon cost as 2MB of non_Z-RAM + the lesser cost when going to 45nm !!

or may AMD postponed the 45nm parts to go with AM3 ??

RE: 45nm, DDR3 or Z-RAM ??
By JackPack on 12/15/2006 4:10:40 AM , Rating: 2
Shanghai will be 65nm. AMD hasn't even been able to hit process nodes on time, so the chance of them pulling in their already aggressive 45nm schedule is remote.

RE: 45nm, DDR3 or Z-RAM ??
By jonnybradley on 12/15/2006 6:28:32 AM , Rating: 2
I thought I read (on DT I think) that K8L would support DDR2 and DDR3, as in the same chip will take either, or am I just being mad?

RE: 45nm, DDR3 or Z-RAM ??
By aka1nas on 12/15/2006 1:18:53 PM , Rating: 3
My understanding was that K8L will have a DDR2/DDR3 mem controller and will technically be a socket AM3 chip. However, it will be keyed in such a way that you can fit it into an AM2 motherboard still and use it with DDR2.

RE: 45nm, DDR3 or Z-RAM ??
By KristopherKubicki on 12/15/2006 3:17:31 PM , Rating: 2
RE: 45nm, DDR3 or Z-RAM ??
By Xajel on 12/15/2006 11:29:23 PM , Rating: 2
even if K8L will support both DDR2/3, there will be no support in the real word, the current roadmap stated that DDR3 support is being slated to mid 08, and for this mean, the AM3 Socket will delaid for that time too ( as AM3 = DDR3 ), K8L still on it's time in 3Q07 and some source says it may be late Q2 for some chips ( mostly Opterons )

So I guess the first K8L will be in AM2+ mobos, ( and will work on AM2 mobos with some features disabled, HT3 + split power lanes are my main guess ) after that in 9 months ( to mid 08 ) we will have DDR3 with AM3...

the problem is to said that Shanghai are dated for earlier than mid 2008, so what Shanghai will have ??

if DDR3 & 45nm are scheduled for mid08 and K8L for Q3-07 so what we are guessing for Shanghai ??

is Z-RAM ?? 2MB of L3 will go for 10MB if Z-RAM is used, this assueming AMD will use the same silicon area.

RE: 45nm, DDR3 or Z-RAM ??
By Xajel on 12/15/2006 11:10:37 PM , Rating: 2
AMD-IBM stated they will go for 45nm in 18 months started from the first 65nm round up, counting from this month, this will end at late 1H08...

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