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AMD executives reveal more cache, more quad-core en route for AMD

Over the last few months much as been revealed about AMD's next-generation quad-core architecture.  This architecture, previously dubbed K8L by Henri Richard, now publically dubbed K10, is scheduled to be the first monolithic quad-core design. AMD engineers still internally refer to this architecture as Greyhound.

Since unveiling the details of the chip, AMD has started to use the codename Barcelona to describe the server variant. The Barcelona chipset is a member of the Cities family -- all server-based AMD codenames for 2007 and 2008 are named after Cities. Desktop codenames are all named after Stars even though architecturally, many Stars and Cities CPUs are identical.

AMD has revealed to DailyTech that Barcelona, which AMD just recently demonstrated, will be "enhanced" with the Shanghai core in early 2008.  AMD's Senior Vice President, Marty Seyer, would not elaborate on what the enhancements are, claiming that the new core would simply "bring further performance enhancements, as well as cache efficiency." 

When the Greyhound architecture was publically unveiled this past June, AMD's Corporate Vice President and CTO Phil Hester claimed that the initial Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K10 with larger caches are roadmap possibilities. Although we cannot speak for the other enhancements, the additional cache Hester described in June 2006 is almost certainly present in Shanghai.

As with previous generations of Opteron processors, Barcelona will only encompass the multi-socket codename. For single-socket servers, Budapest will act as AMD's city codename for the 1xxx Opteron processor.  There is no "cache-upgrade" version of Budapest in the way that Shanghai is an upgrade for Barcelona.  This is likely due to the fact that whatever enhancements are on Shanghai do not necessarily show performance gains on single-socket systems.

According to AMD's roadmaps, Shanghai will still utilize DDR2 memory, though DDR3 processors are also slated for production around that time as well.  "DDR2 is going to serve us quite nicely for several years," added Seyer.



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Cache
By JackPack on 12/14/2006 6:58:02 PM , Rating: 1
quote:
Barcelona processor would utilize 2MB of L3 shared cache -- hinting that additional versions of K8L with larger caches are roadmap possibilities


Given that Barcelona only has 512 KB of L2 per core, I sure as heck hope a larger L3 is on the horizon.




RE: Cache
By ADDAvenger on 12/14/2006 7:10:02 PM , Rating: 3
AMD doesn't need nearly as much L2 because of their IMC. I do realize that in some cases there's simply no substitute for cache, but that doesn't seem to be so in most cases.


RE: Cache
By nerdye on 12/14/2006 9:38:24 PM , Rating: 2
That is true that the IMC makes extra cache almost trivial on the current 939 and am2 amd processors, yet some tasks are simply very cache sensitive and amd suffers in those small cases. We are assuming that amd's archtecture will be similar enough that the less cache on an amd processor arguement will still be valid, which I also support. I honestly don't think that amd running ddr3 will help them that much right away, yet will allow their chipsets to mature during the transition period in the market (which will be very slow) from ddr2 to ddr3, just as intel matured their ddr2 chipsets all while there was still a huge market for ddr1 which amd was still using primarliy at the time. We all know that amd is gaining ground in the server market due to multi socket systems ala hypertransport, I and all of us nerds for that matter should hope amds stars/desktop processors carry on that trend, in the light of good competition to core 2 duo, which I just bought last week by the way.


RE: Cache
By ChipDude on 12/17/2006 1:21:04 AM , Rating: 2
AMD can talk all the want about cache, LOL. Their problem is they don't have 4 fabs running tens of thousands of wafers a week. So, in the end they'd like cache, but they don't got capacity... Poor AMD.

If INTEL didn't put 4 Meg of cache and instead increased the CPU count by 30% we'd be seeing 50 dollar Core2s or INTEL would be laying off more people. In the end this cache argument is very academic. Both companies lock and load their architectures years ahead, cacluate total CPU market, aim for a market share and put factories in place. Nobody just says lets expand from 2-4Meg or vice versa.

If AMD puts a lot of cache on Barcelona it will cost them valuable silicon. Either they concede market share or give something else up.


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