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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

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RE: AMD vs INTEL technology
By joset00 on 12/16/2006 8:33:33 PM , Rating: 2
(OT), not to mention that:

1. Immersion Lithography is not mature, yet (and, AMD seems to have a lot of 'immature' techniques on the way...);

2. DSL helps... in IBM/AMD's SOI process; and costs a lot & adds delay to manufacturing, also;

3. 'Porous ultra-low-k dielectric interconnects' usually have this complex drawback: poor thermal conduction. Counter measures add up to production delay & overall costs.

Well done.


RE: AMD vs INTEL technology
By ChipDude on 12/17/2006 1:11:44 AM , Rating: 2
LOL; Ultra low K is like building the backend system with a house of cards. If you aren't carefuly your house of cards will collapse once you put your hot chip into a package.

I can only laugh at the last time IBM made all this noise about breakthru in LowK with SILK then to see what happenend to their poor customers.

DSL is very expensive, takes probably two extra litho layers, depositions and some etch or fancy selective implants. All expensive extra steps, yield degradation, and I can't wait to see the reverse engineering pictures of it in real production. Its funny that you see it in their papers but never in their products yet.

RE: AMD vs INTEL technology
By joset00 on 12/17/2006 1:53:10 PM , Rating: 2
Yep, the [actual] trend seems to go with high-k metal dielectrics and increased gate oxide thickness (tox), for leakage 'screening'; sometimes (and, this s appears to be the case, for some), one's led to confusion, on what concerns transistor process & interconnects; actually, IBM/AMD are addressing 'porous UL-k dielectrics' in interconnects, not in the gate oxide.
SOI is a promising technique, process-wise; however, the way it's being implemented right now, in chip's substrates, is way too costly, requires Dual-Stress Liners, spacers and it doesn't solve juction leakage.
Intel's aiming at using Fully-Depleted SOI, whenever it finds necessary; the most interesting of all is that Intel's achieving extraordinary results in its process manufacturing, stiking with 'plain old technology', namely, off-the-shelf bulk silicon & dry lithography, for instance. That, in itself, is quite an achievement! And, with that, it's gone down into the 65nm [mature] node without much hassles. Compared to IBM/AMD actual 90nm, yields are far higher & reliable (RAS), even with massive amounts of L2 cache.
In my opinion (and considering data available), AMD might really bring up significant increases in drive current, especially in pMOS... compared to its previous process, not Intel's. And, that still leaves power dissipation & leakage issues out of the equation...


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