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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.



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By drebo on 12/13/2006 3:46:44 PM , Rating: 2
What's more important than this, though, is that once you get to a certain size, you can no longer distinguish between an open gate and a closed gate...they simply all allow current to flow. That is the true boundry for how small we can go. If I remember correctly, it's something like 12nm, but I could be wrong.


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